IP Library Granted Patent US 7,471,098
Granted Patent B2
US 7,471,098 · App. 10/975,663 · Granted Dec 30, 2008

Testing device and method for an integrated circuit

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Quick Facts
Patent No.
US 7,471,098
App. No.
10/975,663
Granted
Dec 30, 2008
Kind
B2
Abstract

An apparatus and method are provided for testing integrated circuits. An integrated circuit arrangement is provided having first and second dice. Each die has circuitry for diagnostic testing in response to a diagnostic test signal. The circuitry further defines an input for receiving the diagnostic test signal and an output for transmitting results of the diagnostic testing for each of the dice. Interconnecting circuitry between the dice transmits the diagnostic test signal transmitted to the first die to the second die before the diagnostic testing is completed in the first die.

Claims (22)

1. A method for testing an integrated circuit comprising:

processing a first die and a second die, each comprising diagnostic testing circuitry responsive to a diagnostic test signal;

transmitting the diagnostic test signal to the first die; and

subsequently transmitting the diagnostic test signal from the first die to the second die before diagnostic testing of the first die is completed.

2. The method of claim 1 comprising:

processing a third die and a fourth die, each comprising diagnostic testing circuitry responsive to the diagnostic test signal;

transmitting the diagnostic test signal to the first die and the third die;

subsequently transmitting the diagnostic test signal to the second die and the fourth die while simultaneously performing the diagnostic testing of the first die and the third die.

3. The method of claim 1 wherein the subsequently transmitting step is characterized by interconnecting circuitry between the dice that is disposed with the dice in a wafer substrate.

4. The method of claim 2 wherein the simultaneously transmitting step is characterized by a probe operably matingly engaging the dice for transmitting the diagnostic test signal to the first die and the third die.

5. The method of claim 2 wherein the transmitting steps comprise:

matingly engaging the dice with a probe for transmitting the diagnostic test signal to the first die and for receiving results of diagnostic testing from the second different die;

moving the probe; and

matingly engaging the dice with the probe for transmitting the diagnostic test signal to the third die and receiving the results of diagnostic testing from the fourth die.

6. The method of claim 4 wherein the subsequently transmitting step is characterized by interconnecting circuitry between the dice that is disposed in the probe.

7. The method of claim 1 comprising qualifying the dice in response to results of diagnostic testing from the dice.

8. The method of claim 1 comprising transmitting the results of diagnostic testing from the second die to the first die.

9. An arrangement for testing an integrated circuit comprising:

first and second dice, each comprising circuitry capable of diagnostic testing in response to a diagnostic test signal, the circuitry defining an input for receiving the diagnostic test signal and an output for transmitting results of the diagnostic testing for each of the dice;

interconnecting circuitry between the dice transmitting the diagnostic test signal transmitted to the first die to the second die before the diagnostic testing is completed in the first die; and

turn around circuitry that transmits the results of the diagnostic testing from the second die to the first die, the first die comprising the input and the output.

10. The arrangement of claim 9 further comprising a third die interconnected between the first and second dice.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jul 23, 2025
From: THE BANK OF NOVA SCOTIA
To: SEAGATE TECHNOLOGY PUBLIC LIMITED COMPANY; SEAGATE TECHNOLOGY; SEAGATE TECHNOLOGY HDD HOLDINGS; I365 INC.; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE HDD CAYMAN; SEAGATE TECHNOLOGY (US) HOLDINGS, INC.
Reel/Frame 072193/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jul 19, 2013
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT AND SECOND PRIORITY REPRESENTATIVE
To: SEAGATE TECHNOLOGY LLC; EVAULT INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE TECHNOLOGY US HOLDINGS, INC.
Reel/Frame 030833/0001 →
SECURITY AGREEMENT Recorded Mar 24, 2011
From: SEAGATE TECHNOLOGY LLC
To: THE BANK OF NOVA SCOTIA, AS ADMINISTRATIVE AGENT
Reel/Frame 026010/0350 →
RELEASE Recorded Jan 19, 2011
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SEAGATE TECHNOLOGY HDD HOLDINGS; MAXTOR CORPORATION; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL
Reel/Frame 025662/0001 →
SECURITY AGREEMENT Recorded May 15, 2009
From: MAXTOR CORPORATION; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND FIRST PRIORITY REPRESENTATIVE; WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT AND SECOND PRIORITY REPRESENTATIVE
Reel/Frame 022757/0017 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2005
From: WARREN, ROBERT W.; HUELSKAMP, PAUL J.
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 016221/0514 →