IP Library Granted Patent US 7,500,129
Granted Patent B2
US 7,500,129 · App. 10/976,572 · Granted Mar 3, 2009

Adaptive communication interface

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Quick Facts
Patent No.
US 7,500,129
App. No.
10/976,572
Granted
Mar 3, 2009
Kind
B2
Abstract

Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate.

Claims (19)

1. A device comprising:

a first storage device having a first communication capacity coupled to a second storage device having a second communication capacity over a communication medium, wherein the first and second communication capacities differ from one another;

a signaling module coupled to the first storage device, the signaling module to signal one of an initiation of data transfer on a request line or an acknowledgement of received data on an acknowledgement line, the signaling module to throttle the rate of transfer over the communication medium; and

a control module coupled to the first storage device, the control module to provide a read or write signal to the first storage device, wherein the control module receives a control signal to initiate the read or write signal and a delayed version of the control signal to end the read or write signal.

2. The device of claim 1 further comprising:

a sequence generator to transmit a data sequence to be used to determine a delay time necessary to achieve a desired error bit rate.

3. The device of claim 1 , further comprising:

a correlator to receive a known data sequence and determine a delay time necessary to achieve a desired error bit rate.

4. The device of claim 1 , further comprising:

a synchronizing circuit to synchronize one of a request and acknowledge a signal to a clock domain of the device.

5. The device of claim 1 , wherein the signaling module comprises:

a latch that is enabled if the first storage device has receiving capacity.

6. The device of claim 1 , further comprising:

a delay module to delay an incoming signal based on the time necessary to compensate for skew and distortions over the communication medium.

7. The device of claim 1 , wherein the request signal and acknowledge signal are non return to zero signals.

8. An apparatus, comprising:

a first device having a first communication capacity to communicate with a second device having a second communication capacity over a communication medium, wherein the first and second communication capacities differ from one another;

a signaling module coupled to the first device, the signaling module to signal one of an initiation of data transfer on a request line and an acknowledgement of received data on an acknowledgement line, the signaling module to throttle the rate of transfer over the communication medium; and

a control module coupled to the first device, the control module to provide a read or write signal to the first device, wherein the control module receives a control signal to initiate the read or write signal and a delayed version of the control signal to end the read or write signal.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2012
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027632/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2012
From: INTEL CORPORATION
To: NUMONYX B.V.
Reel/Frame 027545/0314 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2004
From: HOFFMAN, JEFFREY D.; BJERKE, ALLAN R.
To: INTEL CORPORATION
Reel/Frame 015944/0507 →