Partitioned integrated circuit package with central clock driver
View Patent ↗Disclosed are IC partitioned packaging and interconnection constructions that provide for improved distribution of power, ground, cross chip interconnections and clocks.
1. An integrated circuit (IC) package assembly comprising a subassembly that includes:
a) an IC die with a first surface having a central surface region, a peripheral surface region extending from the central surface region to a periphery of the first surface, and a plurality of central terminals disposed on the central surface region; and
b) a first interconnection redistribution substrate having redistribution circuitry required for the operation of the IC die and a plurality of conductive wires electrically coupled with a corresponding central terminal to form a subassembly, said interconnection redistribution substrate having planar dimensions less than those of the first surface of the IC die such that at least some of the peripheral surface region of the first surface is exposed.
2. The integrated circuit (IC) package assembly of claim 1 , wherein the redistribution circuitry is selected from among a group of circuits consisting of cross-chip circuits configured to couple first and second electrical elements within said IC die, power distribution circuits, clock distribution circuits, ground distribution circuits, and combinations thereof.
3. The integrated circuit (IC) package assembly of claim 1 further comprising a second interconnection redistribution substrate electrically interconnected with the subassembly.
4. The integrated circuit (IC) package assembly of claim 3 further comprising a plurality of peripheral terminals disposed on the peripheral surface region of the subassembly, a plurality of conductive bond sites disposed on said second interconnection redistribution substrate, and a first plurality of wire bonds, each of the first plurality of wire bonds coupling a peripheral terminal to a corresponding conductive bond site.
5. The integrated circuit (IC) package assembly of claim 4 wherein the second interconnection redistribution substrate comprises a plurality of parallel surfaces forming at least one stairstep formation, and wherein the first plurality of bond sites are disposed on at least two of said plurality of parallel surfaces forming said at least one stairstep formation.
6. The integrated circuit (IC) package assembly of claim 5 wherein the second interconnection redistribution substrate further comprises a metal bond pad, and wherein the subassembly is disposed on the metal bond pad.
7. The integrated circuit (IC) package assembly of claim 6 further comprising a die attach adhesive formed on the metal bond pad and coupling the subassembly thereto.
8. The integrated circuit (IC) package assembly of claim 6 wherein the metal bond pad is disposed on a layer that extends to form a bottom layer within said at least one stairstep formation.
9. The integrated circuit (IC) package assembly of claim 8 wherein said at least stairstep formation includes facing stairstep regions that form a stairstep well between said facing stairstep regions, and wherein said subassembly is disposed within said stairstep well.
10. The integrated circuit (IC) package assembly of claim 4 wherein the redistribution substrate further comprises apertures having conductive members disposed therein.
11. The integrated circuit (IC) package assembly of claim 10 further comprising a second plurality of bond wires, at least one of the second plurality of bond wires electrically coupling one of the conductive members within an aperture to a bond site on said at least one stairstep formation.
12. The integrated circuit (IC) package assembly of claim 4 wherein the plurality of conductive wires that couple the first redistribution substrate to the first IC die comprise at least two different lengths of conductive wire.