Dual function FinFET, finmemory and method of manufacture
View Patent ↗A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.
1. A nonvolatile storage device comprising:
a semiconductor fin formed on a dielectric surface;
a control gate along one side of said fin;
a floating gate along an opposite side of said fin; and
a program gate adjacent to said floating gate.
2. A nonvolatile storage device as in claim 1 , wherein said semiconductor fin selected from a group of materials consisting of silicon, germanium and silicon-germanium.
3. A nonvolatile storage device as in claim 2 , wherein said fin is a silicon fin.
4. A nonvolatile storage device as in claim 3 , further comprising:
a gate dielectric layer on both of said silicon fin, said control gate and said floating gate being separated from said silicon fin by said gate dielectric layer.
5. A nonvolatile storage device as in claim 4 , wherein said gate dielectric layer is an oxide layer.
6. A nonvolatile storage device as in claim 1 , wherein said control gate and said floating gate are doped polysilicon.
7. A nonvolatile storage device as in claim 1 , wherein said dielectric surface is the surface of a buried oxide layer in a silicon on insulator (SOI) wafer.
8. A nonvolatile storage device comprising:
a semiconductor fin formed on a dielectric surface;
a control gate along one side of said fin;
a floating gate along an opposite side of said fin, wherein said control gate and said floating gate are doped polysilicon; and
a program gate adjacent to said floating gate, wherein said program gate is doped silicon germanium (SiGe).
9. A nonvolatile storage device as in claim 8 , further comprising a high K dielectric layer separating each of said SiGe program gates from a corresponding said floating gate.
10. A nonvolatile storage device as in claim 8 , wherein said semiconductor fin selected from a group of materials consisting of silicon, germanium and silicon-germanium.
11. A nonvolatile storage device as in claim 10 , wherein said fin is a silicon fin, said nonvolatile storage device further comprising:
a gate dielectric layer on both sides of said silicon fin, said control gate and said floating gate being separated from said silicon fin by said gate dielectric layer.
12. A nonvolatile storage device as in claim 11 , wherein said gate dielectric layer is an oxide layer.
13. A nonvolatile storage device as in claim 8 , wherein said dielectric surface is the surface of a buried oxide layer in a silicon on insulator (SOI) wafer.
14. A nonvolatile storage device as in claim 8 , wherein said dielectric surface is the surface of an oxide layer disposed on a nitride layer in a bonded silicon on insulator (SOI) wafer.
15. A nonvolatile storage device comprising:
a silicon fin formed on a surface of an oxide layer disposed on a nitride layer in a bonded silicon on insulator (SOI) wafer;
a control gate along one side of said silicon fin;
a floating gate along an opposite side of said silicon fin; and
a program gate adjacent to said floating gate.
16. A nonvolatile storage device as in claim 15 , further comprising:
a gate dielectric layer on both sides of said silicon fin, said control gate and said floating gate being separated from said silicon fin by said gate dielectric layer.
17. A nonvolatile storage device as in claim 16 , wherein said gate dielectric layer is an oxide layer.
18. A nonvolatile storage device as in claim 15 , wherein said program gates are doped silicon germanium (SiGe).
19. A nonvolatile storage device as in claim 18 , wherein said program gates are doped silicon germanium (SiGe).
20. A nonvolatile storage device as in claim 19 , further comprising a high K dielectric layer separating each of said SiGe program gates from a corresponding said floating gate.