Stacked memory, memory module and memory system

1. A stacked memory comprising:

a package substrate having signal terminals arranged near the periphery thereof, and

a plurality of memory chips that are mounted on both surfaces of said package substrate and share said signal terminals; and

a wiring in said package substrate that connects said signal terminals to said plurality of memory chips,

wherein said wiring has a substantially equal length between at least one of said signal terminals and a pair of said plurality of memory chips.

2. The stacked memory according to claim 1 , wherein at least one of said plurality of memory chips has chip pads arranged near the periphery thereof to connect to said wirings formed in said package substrate.

3. The stacked memory according to claim 1 , further comprising a code set-up device for setting in an active state, one of the plurality of memory chips in accordance with a code of an externally supplied chip select signal of a plurality of bits.

4. The stacked memory according to claim 3 , wherein said code set-up device comprises:

a jumper chip on which a jumper wiring is mountable for supplying a power-supply voltage or a ground potential, and

a decode circuit for decoding said chip select signal in accordance with an output potential of said jumper chip and supplying a decoded result to each of said plurality of memory chips.

5. A stacked memory comprising:

a package substrate having signal terminals arranged near the periphery thereof, and

a plurality of memory chips that are mounted on both surfaces of said package substrate and share said signal terminals

a code set-up device for setting in an active state, at least one of said plurality of memory chips in accordance with a code of an externally supplied chip select signal of a plurality of bits,

wherein said code set-up device comprises:

a jumper chip on which a fuse for supplying a power-supply voltage or a ground potential is mounted in a fusible arrangement, and

a decode circuit for decoding said chip select signal in accordance with an output potential of said jumper chip and supplying a decoded result to at least one of said plurality of memory chips.

6. A stacked memory comprising:

a plurality of memory chips provided with through holes for wiring, and

a package substrate on which said plurality of memory chips are stacked on one surface thereof, and provided with a directional coupler that supplies a signal to said plurality of memory chips from signal terminals shared by said plurality of memory chips.

7. The stacked memory according to claim 6 , further provided with a signal terminal for supplying another signal arranged between two said signal terminals connected to said directional coupler.

8. The stacked memory according to claim 6 , wherein said memory chip is provided with a driver-terminator circuit that serves as both a driver circuit for providing a data output and a terminator circuit for terminating a wiring end when receiving data.

9. A memory module comprising:

stacked memories according to claim 6 , and

a module substrate provided with a point-to-point bus and a daisy chain bus for carry signals to said stacked memories, wherein said stacked memories are mounted on each of both surfaces of said module substrate spaced apart by a distance equivalent to a length of at least one stacked memory.

10. The memory module according to claim 9 , configured in a four-rank configuration in which four memory chips are set in an active state at the same time.

11. The memory module according to claim 9 , wherein a connection point that connects said daisy chain bus and a stacked memory mounted on one surface of said module substrate and the connection point that connects said daisy chain bus and a stacked memory mounted on another surface of said module substrate are different points.

12. A memory system, comprising:

memory modules each according to claim 9 ,

slots in which said memory modules are to be installed, and

a memory controller that is connected independently to said memory modules and enables simultaneous access to a plurality of said memory modules.

13. A stacked memory comprising:

a package substrate having signal terminals arranged near a periphery thereof; and

a plurality of memory chips that are mounted on both surfaces of said package substrate and share said signal terminals,

wherein at least one of said plurality of memory chips is provided with a driver-terminator circuit that serves as both a driver circuit for providing a data output and a terminator circuit for terminating a wiring end when receiving data.

14. A memory module comprising:

stacked memories comprising:

a package substrate having signal terminals arranged near the periphery thereof, and

a plurality of memory chips that are mounted on both surfaces of said package substrate and share said signal terminals; and

a module substrate provided with a point-to-point bus and a daisy chain bus for carry signals to said stacked memories, wherein said stacked memories are mounted on each of the front and reverse surfaces spaced apart by a distance equivalent to a length of at least one stacked memory.

15. The memory module according to claim 14 , wherein each wiring of a chip select signal for setting said plurality of memory chips in an active state is connected to said stacked memories such that said plurality of memory chips provided in the stacked memories mounted on one surface are selected at the same time alternately with said plurality of memory chips provided in the stacked memories mounted on another surface of said module substrate.

16. The memory module according to claim 14 , configured in a four-rank configuration in which four memory chips are set in an active state at the same time.

17. The memory module according to claim 14 , wherein a connection point that connects said daisy chain bus and a stacked memory mounted on one surface of said module substrate and a connection point that connects said daisy chain bus and a stacked memory mounted on another surface of said module substrate are different points.

18. A memory system, comprising:

memory modules each according to claim 14 ,

slots in which said memory modules are to be installed, and

a memory controller that is connected independently to said memory modules and enables simultaneous access to a plurality of said memory modules.

19. A memory module comprising:

stacked memories comprising:

a package substrate having signal terminals arranged near the periphery thereof,

a plurality of memory chips that are mounted on both surfaces of said package substrate and share said signal terminals, and

a code set-up device for setting in an active state, at least one of said plurality of memory chips in accordance with a code of an externally supplied chip select signal of a plurality of bits; and

a module substrate provided with a point-to-point bus and a daisy chain bus for carrying signals to said stacked memories, wherein said stacked memories are mounted on each of the front and reverse surfaces spaced apart by a distance equivalent to a length of at least one stacked memory.

20. The memory module according to claim 19 , wherein a chip select signal for setting said plurality of memory chips in an active state is supplied to each of stacked memories such that said plurality of memory chips provided in the stacked memories mounted on one surface of said module substrate are selected at the same time alternately with said plurality of memory chips provided in the stacked memories mounted on another surface of said module substrate.

21. The memory module according to claim 19 , configured in a four-rank configuration in which four memory chips are set in an active state at the same time.

22. The memory module according to claim 19 , wherein a connection point that connects said daisy chain bus and a stacked memory mounted on one surface of said module substrate and the connection point that connects said daisy chain bus and a stacked memory mounted on another surface of said module substrate are different points.

23. A memory system, comprising:

memory modules each according to claim 19 ,

slots in which said memory modules are to be installed, and

a memory controller that is connected independently to said memory modules and enables simultaneous access to a plurality of said memory modules.

24. A memory module comprising:

stacked memories each having: a plurality of memory chips provided with through holes for wiring; and

a package substrate on which said plurality of memory chips are stacked on one surface thereof and provided with a plurality of signal terminals for supplying signals to said stacked memories; and

a module substrate provided with a point-to-point bus and a daisy chain bus for carrying signals to said stacked memories,

wherein said stacked memories are mounted on each of both surfaces of said module substrate spaced apart by a distance equivalent to the length of at least one stacked memory, and also provided with a directional coupler for coupling said daisy chain bus and the signal terminals of said stacked memories.

25. The memory module according to claim 24 , configured in a four-rank configuration in which four memory chips are set in an active state at the same time.

26. The memory module according to claim 24 , wherein a connection point that connects said daisy chain bus and a stacked memory mounted on one surface of said module substrate and the connection point that connects said daisy chain bus and a stacked memory mounted on another surface of said module substrate are different points.

27. A memory system, comprising:

memory modules each according to claim 24 ,

slots in which said memory modules are to be installed, and

a memory controller that is connected independently to said memory modules and enables simultaneous access to a plurality of said memory modules.