Efficient method of data transfer between register files and memories

1. A memory system comprising:

an active storage circuit; and

at least one base storage circuit coupled to the active storage circuit through at least one pass gate, at least one driver and a bit line, wherein the at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of a plurality of devices in the active storage circuit and the at least one base storage circuit, wherein the at least one pass gate includes at least one save pass gate and at least one restore pass gate.

2. The memory system of claim 1 , wherein the memory system is included in a microprocessor.

3. The memory system of claim 1 , wherein the at least one restore pass gate has a device size substantially similar to a device size of each one of a plurality of devices in the active storage circuit and the at least one base storage circuit and wherein the at least one save pass gate has a device size sufficient to overcome a parasitic read operation.

4. The memory system of claim 1 , further comprising a pre-charge circuit coupled to the at least one bit line.

5. The memory system of claim 1 , further comprising a keeper circuit coupled to the at least one bit line.

6. The memory system of claim 1 , further comprising a timing and control circuit coupled to the at least one bit line.

7. The memory system of claim 1 , wherein the at least one base storage circuit includes a plurality of base storage circuits and wherein each one of the plurality of base storage circuits corresponds to a processing thread in a multi-thread processor.

8. A memory system comprising:

an active storage circuit having a first active node and a second active node;

a plurality of base storage circuits, each one of the base storage circuits including a corresponding first base node and a corresponding second base node;

a first bit line coupled between the first active node and each one of the plurality of first base nodes, the first bit line including a first save pass gate and a first save driver coupled in series to the first node and a first restore pass gate and a first restore driver coupled in series to the first node; and

a second bit line coupled between the second active node and each one of the plurality of second base nodes, the second bit line including a second save pass gate and a second save driver coupled in series to the second node and a second restore pass gate and a second restore driver coupled in series to the second node, wherein the first save pass gate, the first save driver, the first restore pass gate, the first restore driver, the second save pass gate, the second save driver, the second restore pass gate and the second restore driver have a device size substantially similar to a device size of each one of a plurality of devices in the active storage circuit and the plurality of base storage circuits.

9. Method of swapping data between two storage circuits comprising:

activating a first pass gate between a first storage circuit and a first bit line wherein the first pass gate is a save pass gate and wherein the save pass gate is activated at least a first time delay before the second pass gate is activated;

activating a second pass gate between a second storage circuit and the first bit line;

driving the data stored in the first storage circuit to the first bit line; and

storing the data on the first bit line in the second storage circuit.

10. The method of claim 9 , wherein driving the data stored in the first storage circuit to the first bit line includes amplifying the data stored in the first storage circuit in an amplification circuit having device sizes substantially equal to the devices in the first storage circuit and the second storage circuit.

11. The method of claim 9 , wherein driving the data stored in the first storage circuit to the first bit line includes amplifying the data stored in the first storage circuit in an amplification circuit having device sizes sufficient to overcome a parasitic read operation.

12. The method of claim 9 , wherein the first time delay is equal to about two gate delays.

13. The method of claim 9 , wherein the first time delay is sufficient to allow a sufficient voltage differential to be developed on the first bit line.

14. The method of claim 9 , further comprising applying a keeper circuit to the first bit line.

15. The method of claim 9 , wherein the first storage circuit is an active storage circuit and the second storage circuit is a base storage circuit and wherein the base storage circuit includes a plurality of base storage circuits and wherein each one of the plurality of base storage circuits corresponds to a processing thread in a multi-thread processor.

16. Method of performing a data swap in a multi-threaded microprocessor comprising:

activating a first active pass gate between a first node of an active storage circuit and a first bit line and activating a second active pass gate between a second node of the active storage circuit and a second bit line;

activating a first base pass gate between a first node of a base storage circuit and the first bit line, wherein the first pass gate is a save pass gate and wherein the save pass gate is activated at least a first time delay before the second pass gate is activated, and activating a second base pass gate between a second node of a base storage circuit and the second bit line;

driving the data stored in the active storage circuit to the first bit line and the second bit line; and

storing the data on the first bit line and the second bit line in the base storage circuit.

17. The method of claim 16 , wherein the base storage circuit is one of a plurality of base storage circuits coupled to the first bit line and the second bit line and wherein each one of the plurality of base storage circuits corresponds to one of a plurality of processing threads and wherein activating the first base pass gate and activating the second base pass gate includes receiving a thread select control signal that corresponds to a selected process thread and a corresponding base storage circuit.