Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof
View Patent ↗A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.
1. A manufacturing method of an electrically erasable programmable read-only memory (EEPROM) cell, comprising:
providing a substrate;
forming a first well region and a second well region, with difference conductive type each other, in the substrate;
forming a tunnel layer and an inter-gate dielectric layer over a surface of the substrate respectively;
forming a doped region used as a control gate in the substrate under the inter-gate dielectric layer;
forming a floating gate over the inter-gate dielectric layer and the tunnel layer, wherein the floating gate is formed over the first well region and the second well region; and
forming a source region and a drain region in the substrate beside two sides of the floating gate under the tunnel layer.
2. The method of claim 1 , wherein a thickness of the inter-gate dielectric layer is greater than a thickness of the tunnel layer.
3. The method of claim 1 , wherein a thickness of the inter-gate dielectric layer is in a range of about 30 nm to about 50 nm.
4. The method of claim 1 , wherein the tunnel layer is formed on a surface of the first well region, the inter-gate dielectric layer is formed on a surface of the second well region, and the doped region used as the control gate is formed in the second well region.
5. The method of claim 1 , wherein a method of forming the tunnel layer and the inter-gate dielectric layer comprises:
forming a dielectric material layer over the substrate;
removing a portion of the dielectric material layer to form an exposed substrate, wherein a residual portion of the dielectric material layer comprises the inter-gate dielectric layer; and
forming a tunnel layer over the exposed substrate.
6. The method of claim 1 , wherein a method of forming the source region and the drain region comprises:
forming a deeply doped region in the substrate corresponding to one side of the floating gate and under the tunnel layer; and
forming the source region and the drain region in the substrate at two sides of the floating gate and under the tunnel layer, wherein the source region is formed in the deeply doped region.
7. The method of claim 1 , further comprising forming a densely doped region in the doped region used as the control gate.