IP Library Granted Patent US 7,319,623
Granted Patent B1
US 7,319,623 · App. 10/981,026 · Granted Jan 15, 2008

Method for isolating a failure site in a wordline in a memory array

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Quick Facts
Patent No.
US 7,319,623
App. No.
10/981,026
Granted
Jan 15, 2008
Kind
B1
Abstract

According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordline portion has wordline-to-substrate leakage. The initial leaky wordline portion can be determined by using a passive voltage contrast procedure to illuminate the initial leaky wordline portion. The method further includes performing a number of division and identification cycles on the initial leaky wordline portion to determine a final leaky wordline portion. According to this exemplary embodiment, the final leaky wordline portion comprises a predetermined number of memory cells. The method further includes performing a cutting and imaging procedure on the final leaky wordline portion to isolate the failure site.

Claims (26)

1. A method for isolating a failure site in a leaky wordline in a memory array, said method comprising:

etching a trench in an interlayer dielectric layer to expose a top surface of said leaky wordline, said leaky wordline comprising wordline-to-substrate leakage;

dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion;

performing a plurality of successive identifications on said initial leaky wordline portion to determine a final leaky wordline portion;

wherein said final leaky wordline portion comprises a predetermined number of memory cells.

2. The method of claim 1 further comprising a step of performing a cutting and imaging procedure to isolate said failure site.

3. The method of claim 2 wherein said cutting and imaging procedure comprises performing a plurality of incremental cuts and a corresponding plurality of images of said incremental cuts across said final leaky wordline portion to isolate said failure site.

4. The method of claim 2 wherein said cutting and imaging procedure comprises performing a cut and a corresponding image of said cut along a length of said final leaky wordline portion to isolate said failure site.

5. The method of claim 1 wherein said step of dividing said leaky wordline comprises using a focused ion beam to cut said leaky wordline.

6. The method of claim 1 wherein said step of performing a plurality of successive identifications comprises forming a plurality of intermediate leaky wordline portions, wherein each of said plurality of intermediate leaky wordline portions comprises a greater number of memory cells than said final leaky wordline portion.

7. The method of claim 1 wherein said failure site causes said wordline-to-substrate leakage.

8. The method of claim 1 wherein said memory array is a flash memory array.

9. The method of claim 1 wherein said predetermined number of memory cells comprises eight memory cells.

10. The method of claim 1 wherein said step of dividing said leaky wordline comprises using a passive voltage contrast procedure to illuminate said initial leaky wordline portion.

11. A method for isolating a failure site in a leaky wordline in a memory array, said method comprising:

dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion;

performing a plurality of successive identifications on said initial leaky wordline portion to determine a final leaky wordline portion;

wherein said final leaky wordline portion comprises a predetermined number of memory cells;

performing a cutting and imaging procedure on said final leaky wordline portion to isolate said failure site, wherein said cutting and imaging procedure comprises performing a plurality of incremental cuts and a corresponding plurality of images of said incremental cuts across said final leaky wordline portion to isolate said failure site.

12. The method of claim 11 wherein said cutting and imaging procedure comprises performing a cut and a corresponding image of said cut along a length of said final leaky wordline portion to isolate said failure site.

13. The method of claim 11 wherein said step of dividing said leaky wordline comprises using a focused ion beam to cut said leaky wordline.

14. The method of claim 11 wherein said step of performing said plurality of successive identifications comprises forming a plurality of intermediate leaky wordline portions, wherein each of said plurality of intermediate leaky wordline portions comprises a greater number of memory cells than said final leaky wordline portion.

15. The method of claim 11 wherein said predetermined number of memory cells comprises eight memory cells.

16. The method of claim 13 wherein said step of dividing said leaky wordline further comprises determining said initial leaky wordline portion by using a passive voltage contrast procedure to illuminate said initial leaky wordline portion.

17. The method of claim 11 wherein each of said successive identifications comprises forming an intermediate wordline portion and causing said intermediate wordline portion to be illuminated if said intermediate wordline portion has said wordline-to-substrate leakage.

18. The method of claim 13 wherein said step of dividing said leaky wordline comprises dividing said leaky wordline into an illuminated wordline portion and a non-illuminated portion, wherein said illuminated wordline portion has said wordline-to-substrate leakage.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2004
From: YUAN, CAIWEN; LI, SUSAN XIA; GRAY, ANDY
To: SPANSION LLC
Reel/Frame 015960/0346 →