IP Library Granted Patent US 7,253,074
Granted Patent B2
US 7,253,074 · App. 10/982,009 · Granted Aug 7, 2007

Temperature-compensated resistor and fabrication method therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,253,074
App. No.
10/982,009
Granted
Aug 7, 2007
Kind
B2
Abstract

A method for forming a temperature-compensated resistor on a semiconductor substrate is provided. A resistor element is formed on the semiconductor substrate. Terminal contacts are formed on the ends of the resistor element. A temperature-compensating configuration is formed, and is selected from an enlarged transverse portion in the resistor element intermediate and spaced from the terminal contacts, and at least one contact pattern along and in contact with the resistor element intermediate and spaced from the terminal contacts.

Claims (26)

1. A method of forming a temperature-compensated resistor, comprising:

forming a resistor on a semiconductor substrate;

forming terminal contacts on the ends of the resistor; and

forming at least first and second temperature-compensating elements at least one on and in the resistor, the first element comprising an enlarged transverse portion in the resistor element intermediate and spaced from the terminal contacts, the first element having an epi thermal resistance associated therewith proportional to a coefficient of resistivity ρ e , the second element comprising at least one contact pattern disposed along and in contact with the resistor, and intermediate and spaced from the terminal contacts; the second element having a contact thermal resistance associated therewith proportional to a coefficient of resistivity ρ c ;

wherein the first and second elements are configured to at least partially offset the respective epi and contact resistances associated therewith as a temperature of the resistor changes.

2. The method of claim 1 , wherein forming the resistor further comprises forming a plurality of the contact patterns disposed along and in contact with the resistor, and intermediate and spaced from the terminal contacts.

3. The method of claim 1 , wherein forming the resistor further comprises forming a plurality of the enlarged transverse portions in the resistor intermediate and spaced from the terminal contacts.

4. The method of claim 1 , wherein forming a the resistor further comprises forming an epitaxial resistor.

5. The method of claim 1 , wherein the semiconductor substrate is a gallium arsenide substrate and the resistor is an epitaxial resistor formed in a gallium arsenide process.

6. A method of forming a temperature-compensated resistor, comprising:

in a gallium arsenide process on a gallium arsenide semiconductor substrate, forming the resistor;

forming metallic terminal contacts on ends of the resistor;

forming at least first and second temperature-compensating elements at least one of on and in the resistor, the first element comprising an enlarged transverse portion in the resistor intermediate and spaced from the metallic terminal contacts, the first element having an epi thermal resistance associated therewith proportional to a coefficient of resistivity ρ e , the second element comprising at least one metallic contact pattern disposed along and in contact with the resistor element, and intermediate and spaced from the metallic terminal contacts, the second element having a contact thermal resistance associated therewith proportional to a coefficient of resistivity ρ c ;

wherein the first and second elements are configured to at least partially offset the respective epi and contact resistances associated therewith as a temperature of the resistor changes.

7. The method of claim 6 , wherein forming the resistor further comprises forming a plurality of enlarged transverse portions in the resistor intermediate and spaced from the metallic terminal contacts.

8. The method of claim 6 , wherein forming the resistor further comprises forming a plurality of metallic contact patterns along and in contact with the resistor, and intermediate and spaced from the metallic terminal contacts.

9. The method of claim 6 , wherein forming a the resistor further comprises forming an epitaxial resistor.

10. A temperature-compensated resistor, comprising:

a resistor disposed on a semiconductor substrate;

terminal contacts disposed on ends of the resistor; and

at least first and second temperature-compensating elements disposed at least one of on and in the resistor, the first element comprising an enlarged transverse portion in the resistor intermediate and spaced from the terminal contacts, the first element having an epi thermal resistance associated therewith proportional to a coefficient of resistivity ρ e , the second element comprising at least one contact pattern disposed along and in contact with the resistor, and intermediate and spaced from the terminal contacts the second element having a contact thermal resistance associated therewith proportional to a coefficient of resistivity ρ c ;

wherein the first and second elements are configured to at least partially offset the respective epi and contact resistances associated therewith as a temperature of the resistor changes.

11. The resistor of claim 10 , wherein the temperature-compensating resistor further comprises a plurality of enlarged transverse portions in the resistor intermediate and spaced from the terminal contacts.

12. The resistor of claim 10 , wherein the temperature-compensating resistor further comprises a plurality of contact patterns disposed along and in contact with the resistor element, and intermediate and spaced from the terminal contacts.

13. The resistor of claim 10 , wherein the resistor further comprises an epitaxial resistor.

14. The resistor of claim 10 , wherein the semiconductor substrate is a gallium arsenide substrate and the resistor is an epitaxial resistor formed in a gallium arsenide process.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →