PLL clock signal generation circuit
A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is further included which detects a state of the reference voltage (output from a filter circuit) and controls a change of a multiple rate of a divider according to a state of the detected reference voltage. The multiple rate control circuit further outputs control signal LPFOUT for changing a multiple rate so that the PLL clock signal generation circuit does not deviate from a region capable of locking when being detected of deviation from the region capable of locking by detecting the state of reference voltage.
1. A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator, at least two dividers, and a multiple rate control circuit, wherein
said multiple rate control circuit detects an upper and a lower limit value of a reference voltage and outputs a control signal to each of the at least two dividers for changing a multiple rate so that said PLL clock signal generation circuit does not deviate from a region capable of locking when being detected of deviation from the region capable of locking by detecting said upper and lower limits of said reference voltage which is an output from said filter circuit.
2. The PLL clock signal generation circuit according to claim 1 , wherein the multiple rate control circuit comprising:
a first Schmitt trigger circuit capable of detecting said reference voltage being higher than an upper limit value of a voltage range capable of locking,
a second Schmitt trigger circuit capable of detecting said reference voltage being lower than a lower limit value of a voltage range capable of locking,
a D flip-flop producing said control signal for increasing a ratio of division of said divider by determining said reference voltage being higher than said higher limit value when the output state of both of said first Schmitt trigger circuit and said second Schmitt trigger circuit are at high level, and
a control circuit resetting said D flip-flop by determining said reference voltage being lower than a lower limit value when the output state of both of said first Schmitt trigger circuit and said second Schmitt trigger circuit are at low level.
3. The PLL clock signal generation circuit according to claim 2 , wherein
each of hysteresis widths of said first Schmitt trigger circuit and said second Schmitt trigger circuit is set above the ripple voltage value overlapping the output voltage of said charge pump circuit.
4. The PLL clock signal generation circuit according to claim 1 , wherein the multiple rate control circuit includes a Schmitt trigger circuit which has a hysteresis suited to remove a ripple voltage associated with an output of the charge pump circuit.