Semiconductor device and method of manufacturing the same
View Patent ↗A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor substrate; forming a dielectric layer on the surface of the semiconductor substrate including the isolation trench; filling the isolation trench with a CVD layer; removing the dielectric layer except a portion in the isolation trench by an etching; sequentially forming an insulating layer and a conductive layer; forming a resist defining a pattern which covers via the conductive layer a portion of the insulating layer in contact with the dielectric layer; and performing an anisotropic etching on the resist to thereby remove a portion of the conductive layer exposing a surface thereof.
1. A method of manufacturing a semiconductor device, comprising:
forming an isolation trench on a surface of a semiconductor substrate;
forming a dielectric layer on said surface of said semiconductor substrate including said isolation trench;
filling said isolation trench;
removing said dielectric layer except a portion in said isolation trench;
sequentially forming an insulating layer and a conductive layer which covers said portion of said dielectric layer within isolation trench;
forming a resist defining a pattern which covers via said conductive layer a portion of said insulating layer which covers said dielectric layer; and
performing an anisotropic etching on said resist to thereby remove a portion of said conductive layer exposing a surface of said semiconductor substrate;
wherein said resist covers via said conductive layer a portion of said insulating layer in contact with said filling.
2. The method as recited in claim 1 , further comprising:
forming said insulating layer in contact with an upper surface of said dielectric layer, said filling and said semiconductor substrate; and
forming said conductive layer in contact with an upper surface of said insulating layer.
3. The method as recited in claim 1 , wherein said resist is provided with a pattern for forming a gate electrode of a transistor.
4. The method as recited in claim 1 , wherein said filling is a polycrystalline silicon layer.
5. The method as recited in claim 1 , wherein said filling is constituted of a same material as said dielectric layer.
6. The method as recited in claim 1 , wherein said dielectric layer is a silicon oxide layer.
7. A method of manufacturing a semiconductor device, comprising:
forming an isolation trench on an upper portion of a semiconductor substrate;
forming a first layer in contact with an upper surface of said semiconductor substrate including an inner wall of said isolation trench;
filling said isolation trench with a second layer;
selectively removing said first layer except a portion in said isolation trench;
forming an insulating layer so as to cover said first layer, said second layer and an upper surface of said semiconductor substrate;
forming a conductive layer so as to cover an upper surface of said insulating layer;
forming a resist defining a pattern which covers via said conductive layer a portion of said insulating layer in contact with said second layer and with said first layer; and
selectively removing an exposed portion of said conductive layer, forming a conductive layer on top of said isolation trench and a gate electrode.
8. The method as recited in claim 7 , wherein said second layer is a CVD layer.
9. The method as recited in claim 7 , wherein a gap defined by side surfaces of said semiconductor substrate and said second layer and a top surface of said first layer in said trench is formed when said first layer is selectively removed; and said gap is filled with said insulating layer and said conductive layer.
10. A method of manufacturing a semiconductor device, comprising:
forming an isolation trench on a surface of a semiconductor substrate;
forming a dielectric layer on said surface of said semiconductor substrate including said isolation trench;
filling said isolation trench;
removing said dielectric layer except a portion in said isolation trench;
sequentially forming an insulating layer and a conductive layer which covers said portion of said dielectric layer within said isolation trench;
forming a resist defining a pattern which covers via said conductive layer a portion of said insulating layer which covers said dielectric layer; and
performing an anisotropic etching on said resist to thereby remove a portion of said conductive layer exposing a surface of said semiconductor substrate;
wherein a portion of the remaining conductive material forms a trench shield which covers said dielectric layer.