IP Library Granted Patent US 7,116,572
Granted Patent B2
US 7,116,572 · App. 10/984,065 · Granted Oct 3, 2006

Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,116,572
App. No.
10/984,065
Granted
Oct 3, 2006
Kind
B2
Abstract

A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Claims (21)

1. A method of providing a reference for a ferroelectric memory comprising:

generating a ferroelectric reference voltage;

digitizing the ferroelectric reference voltage by,

counting up from an initial value;

comparing the count value to the generated ferroelectric reference voltage;

stopping the count once the count value exceeds the generated ferroelectric reference voltage; and

using the final count value as the digitized ferroelectric reference voltage; and

periodically updating the digitized ferroelectric reference voltage.

2. The method of claim 1 further comprising periodically generating the ferroelectric reference voltage.

3. The method of claim 1 wherein generating a ferroelectric reference voltage comprises generating a reference voltage derived from the average of a “P” term and a “U” term.

4. The method of claim 1 wherein generating a ferroelectric reference voltage comprises generating a reference voltage derived from the average of a plurality of “P” terms and a plurality of “U” terms.

5. The method of claim 1 wherein generating a ferroelectric reference voltage comprises generating a reference voltage derived from the charge components of two ferroelectric capacitors.

6. The method of claim 5 further comprising selectively polarizing the two ferroelectric capacitors.

7. The method of claim 1 wherein generating a ferroelectric reference voltage comprises generating a reference voltage derived from the charge components of a plurality of ferroelectric capacitors.

8. The method of claim 7 further comprising selectively polarizing the plurality of ferroelectric capacitors.

9. The method of claim 1 wherein comparing the count value comprises comparing an analog version of the count value to the generated ferroelectric reference voltage.

10. The method of claim 1 wherein the digitized ferroelectric reference voltage is updated about once every millisecond.

11. The method of claim 1 , wherein the step of generating a ferroelectric reference voltage comprises:

alternately poling at least two ferroelectric capacitors; and

transferring the charge from the two ferroelectric capacitors onto a reference line.

12. The method of claim 11 further comprising periodically poling the at least two ferroelectric capacitors.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE Recorded Mar 9, 2015
From: SILICON VALLEY BANK
To: RAMTRON INTERNATIONAL CORPORATION
Reel/Frame 035198/0959 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2012
From: RAMTRON INTERNATIONAL CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 029408/0437 →