Semiconductor memory device and manufacturing method thereof
View Patent ↗An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.
1. A semiconductor memory device comprising:
a semiconductor substrate which includes an active region having a plurality of active column portions extending in a first direction and a plurality of active row portions extending in a second direction substantially orthogonal to the first direction, and isolation portions, wherein the active row portions are arranged between and connected to respective pairs of active column portions and wherein respective concave portions are disposed within each active row portion between corresponding pairs of the active column portions;
a floating gate formed over the semiconductor substrate;
a control gate formed over the floating gate as crossing and extending over the active column portions and the isolation portions;
an interlayer insulating film formed over the active region;
a wiring formed over the interlayer insulating film; and
conductive members arranged and buried within the concave portions, the conductive members pass through the interlayer insulating film and connect to the wiring and to the active row portions between the corresponding pairs of the active column portions.
2. The semiconductor memory device of claim 1 , further comprising a transistor consisting of one of the active column portions, the floating gate, and the control gate.
3. The semiconductor memory device of claim 1 , wherein the concave portions are formed in the active row portions when the floating gate is patterned.
4. The semiconductor memory device of claim 1 , wherein the floating gate and the control gate extend in the second direction.
5. The semiconductor memory device of claim 1 , wherein the floating gate and the control gate are over areas of the semiconductor substrate without the active row portions.
6. The semiconductor memory device of claim 1 , wherein the concave portions are formed in a vicinity of a center of the active row portions.
7. The semiconductor memory device of claim 1 , wherein the concave portions have a bottom surface and side surfaces.
8. The semiconductor memory device of claim 7 , wherein the conductive members are connected to the bottom surface and the side surfaces of the concave portions.
9. A semiconductor memory device comprising:
a semiconductor substrate which includes an active region having a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction, and an isolation region,
wherein each active region row is a semiconductor material, is arranged between active region columns and has a concave portion therein;
a floating gate formed over the semiconductor substrate;
a control gate formed over the floating gate as crossing and extending over the active region columns and the isolation region;
an interlayer insulating film formed over the active region;
a wiring formed over the interlayer insulating film; and
conductive members arranged and buried within the concave portions, the conductive members pass through the interlayer insulating film and connect to the wiring and to the active region.
10. The semiconductor memory device of claim 9 , further comprising a transistor consisting of one of the active region columns, the floating gate, and the control gate.
11. The semiconductor memory device of claim 9 , wherein the floating gate and the control gate extend in the second direction.
12. The semiconductor memory device of claim 9 , wherein the floating gate and the control gate are over areas of the semiconductor substrate without the active region rows.
13. The semiconductor memory device of claim 9 , wherein the concave portions are formed in a vicinity of a center of the active region rows.
14. The semiconductor memory device of claim 9 , wherein the conductive members are connected to the semiconductor material at bottom and side surfaces of the concave portions.