Semiconductor memory device and semiconductor device group
A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
1. A semiconductor integrated circuit device, comprising:
a first CMOS inverter including a first n-channel MOS transistor and a first p-channel MOS transistor connected in series at a first node;
a second CMOS inverter including a second n-channel MOS transistor and a second p-channel MOS transistor connected in series at a second node, said second CMOS inverter forming a flip-flop circuit together with said first CMOS inverter;
a first transfer transistor provided between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line, said first transfer transistor being activated by a selection signal on said word line; and
a second transfer transistor provided between a second bit line and said second node, said second transfer transistor having a second gate electrode connected to said word line, said second transfer transistor being activated by the selection signal on said word line,
said first transfer transistor and said second transfer transistor being formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other,
said first transfer transistor contacting with said first bit line at a first bit contact region on said first device region,
said second transfer transistor contacting with said second bit line at a second bit contact region on said second device region,
wherein said first bit contact region is formed in said first device region such that a center of said first bit contact region is offset toward said second device region, and
wherein said second bit contact region is formed in said second device region such that a center of said second bit contact region is offset toward said first device region.
2. The semiconductor integrated circuit device as claimed in claim 1 , further comprising a non-volatile memory on said semiconductor substrate.
3. The semiconductor integrated circuit device as claimed in claim 1 , wherein said first transfer transistor is activated by a selection signal on said word line and wherein said second transfer transistor is activated by a selection signal on said second word line.
4. The semiconductor integrated circuit device as claimed in claim 1 , wherein said first transfer transistor has said first contact region on said first device region at a side with respect to said first gate electrode and a first contact region forming said first node on said device region at an opposite side with respect to said gate electrode,
wherein said second transfer transistor has said second bit contact region on said second device region at a first side with respect to said second gate electrode and a second contact region forming said second node on said second device region at an opposite side with respect to said second gate electrode,
wherein said first device region has a first width in a part in which said first bit contact region is formed, said first width being larger than a width of a part of said first device region in which said first contact region is formed,
wherein said second device region has a second width in a part in which said second bit line is formed, said second width being larger than a width of a part of said second device region in which said second contact region is formed.
5. The semiconductor integrated circuit device as claimed in claim 1 , wherein said first transfer transistor is activated by a selection signal on said word line and wherein said second transfer transistor being activated by a selection signal on said word line.
6. A semiconductor integrated circuit device, comprising:
a first CMOS inverter including a first n-channel MOS transistor and a first p-channel MOS transistor connected in series at a first node;
a second CMOS inverter formed of a second n-channel MOS transistor and a second p-channel MOS transistor connected with each other at a second node, said second CMOS inverter forming a flip-flop circuit together with said first CMOS inverter;
a first transfer transistor provided between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line, said first transfer transistor being activated by a selection signal on said word line; and
a second transfer transistor provided between a second bit line and said second node, said second transfer transistor having a second gate electrode connected to said word line, said second transfer transistor being activated by the selection signal on said word line,
said first transfer transistor and said second transfer transistor being formed respectively in first and second device regions defined on a semiconductor substrate by a device insulation region so as to extend parallel with each other,
said first transfer transistor contacting with said first bit line at a first bit contact region on said first device region,
said second transfer transistor contacting with said second bit line at a second bit contact region on said second device region,
wherein said first bit contact region is formed in said first device region such that a center of said first bit contact region is offset toward said second device region, and
wherein said second bit contact region is formed such that a center of said second bit contact region is offset toward said first device region,
said first transfer transistor having said first bit contact region on said first device region at a first side with respect to said first gate electrode and a first contact region forming said first node on said first device region at an opposite side with respect to said first gate electrode,
said second transfer transistor having said second bit contact region on said second device region at a first side with respect to said second gate electrode and a second contact region forming said second node on said second device region at an opposite side with respect to said second gate electrode,
said first device region having a first width in a part in which said first bit contact region is formed, said first width being larger than a width of a part of said first device region in which said first contact region is formed,
said second device region having a second width in a part in which said second bit contact region is formed, said second width being larger than a width of a part of said second device region in which said second contact region is formed.
7. The semiconductor integrated circuit device as claimed in claim 6 , wherein said first gate electrode and said second gate electrode are formed of a single conductor pattern crossing said fist and second device regions,
said first and second bit contact regions being formed at a first side of said conductor pattern,
said first and second contact regions being formed at a second side of said conductor pattern.
8. The semiconductor integrated circuit device as claimed in claim 6 , wherein said first transfer transistor has a channel width equal to said first width, said second transfer transistor has a channel width equal to said second width.
9. The semiconductor integrated circuit device as claimed in claim 6 , wherein said first and second device regions have respective linear edges mutually opposing with each other.
10. The semiconductor integrated circuit device as claimed in claim 6 , wherein
said first device region has a first bent part beyond said first contact region such that said first bent part is bent in a direction away from said second device region,
said second device region has a second bent part beyond said second contact region such that said second bent part is bent in a direction away from said first device region,
one of said first n-channel MOS transistor and said first p-channel MOS transistor being formed on said first bent part,
one of said second n-channel MOS transistor and said second p-channel MOS transistor being formed on said second bent part.
11. The semiconductor integrated circuit device as claimed in claim 6 , wherein said first and second device regions are placed symmetrically.