System and method for hydrogen exfoliation gettering

1. A hydrogen (H) exfoliation gettering method for attaching fabricated circuits to receiver substrates, the method comprising:

forming a Si-on-insulator (SOI) substrate with a buried oxide (BOX) layer;

forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions;

implanting a p-dopant into the S/D regions;

forming gettering regions underling the S/D regions;

implanting H in the Si substrate, forming a cleaving plane in the Si substrate about as deep as the gettering regions, with a horizontal peak concentration (Rp) H layer in regions of the Si substrate underlying the S/D regions;

bonding the circuit to a receiver substrate;

cleaving the Si substrate along the cleaving plane by

cleaving a first region along the horizontal Rp layer in the regions underlying the S/D) regions;

cleaving a second region along a horizontal interface between the BOX layer and Si substrate underlying the channel region; and

cleaving vertically between the first and second regions; and

binding the implanted H underlying the S/D regions with p-dopant in the gettering regions.

2. The method of claim 1 further comprising:

performing a post-bond annealing of the Si substrate; and

wherein binding the implanted H with p-dopant in the gettering regions includes binding in response to the post-bond annealing.

3. The method of claim 1 wherein binding the implanted H with p-dopant in the gettering regions includes:

passivating p-dopant in the gettering regions; and

minimizing the passivation of p-dopant in the S/D regions.

4. The method of claim 3 wherein forming a Si active layer overlying the substrate includes forming a channel region with p- dopant, interposed between the S/D) regions;

wherein forming gettering regions includes forming gettering regions adjacent the channel region; and

wherein binding the implanted H with p-dopant in the gettering regions includes minimizing the passivation of p-dopant in the channel region.

5. The method of claim 1 wherein forming a circuit S/D regions in the Si active layer includes forming a circuit at process temperatures greater than 600 degrees C.; and

wherein bonding the circuit to the receiver substrate includes bonding the circuit to a temperature-sensitive carrier substrate selected from the group including glass, plastic, quartz, and metal foil.

6. The method of claim 1 wherein implanting H in the Si substrate includes:

implanting H in a farm selected from the group including H+ and H2;

implanting at a maximum energy of 1 MeV; and

implanting at a dosage in the range of 5×10 16 to 5×10 17 .

7. The method of claim 1 further comprising:

following the H implanting, depositing a top oxide layer overlying the circuit;

planarizing the top oxide layer; and

wherein bonding the circuit to the receiver substrate includes directly bonding the top oxide layer to the receiver substrate.

8. The method of claim 2 wherein cleaving the Si substrate includes cleaving in response to a pre-cleavage annealing of the Si substrate.

9. The method of claim 2 wherein performing a post-bond annealing of the Si substrate includes annealing at a temperature in the range of 400 to 600 degrees C.

10. The method of claim 1 wherein cleaving the Si substrate includes cleaving in response to a mechanical separation process.

11. The method of claim 1 further comprising:

forming a blocking mask overlying the channel region; and

wherein implanting H in the Si substrate includes:

implanting H into the S/D regions, but not the channel region underlying the blocking mask; and

following the H implantation, removing the blocking mask.

12. The method of claim 8 wherein implanting H in the Si substrate includes implanting H in the substrate to the same depth as the furthest penetration of the gettering regions;

wherein pre-cleavage annealing the Si substrate includes annealing at a temperature in the range of 200 to 300 degrees C.; and

wherein cleaving the Si substrate includes cleaving in response to pre-cleavage annealing the Si substrate.

13. The method of claim 1 further comprising:

following the cleaving of the Si substrate, using an ion etch technique, removing any remaining Si substrate material.

14. The method of claim 1 wherein forming circuit S/D regions in the Si active layer includes forming a VLSI device.

15. The method of claim 1 wherein forming gettering regions in the Si substrate includes:

implanting p-dopant with an energy sufficient to penetrate to the level of the cleaving plane; and

implanting at a dosage in the range of 1×10 19 to 5×10 20 atoms/cm 3 .

16. The method of claim 1 wherein forming gettering regions in the Si substrate includes forming gettering regions simultaneously with implanting p-dopant in the S/D regions.

17. The method of claim 1 wherein forming gettering regions underlying the S/D regions includes forming gettering regions using a p-dopant selected from the group including boron, gallium, indium, and aluminum.