Low-power low-voltage multi-level variable-resistor line driver
View Patent ↗A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. This invention discloses the design of a multi-level PAM driver for high-speed wireline communication, with up to four times improvement in power efficiency over conventional drivers. Two key requirements for high-speed line drivers are first generating the target voltage level onto the controlled-impedance line, and second being impedance matched to the line itself to eliminate signal reflections from the transmitter back to the line. The driver in accordance with the present invention satisfies both of these requirements at very high power efficiency.
1. A line driver circuit including a first output terminal and a second output terminal, the line driver circuit comprising:
a first pull-up variable resistor and a first switch connected in series between a first power supply and the first output terminal;
a second pull-up variable resistor and a second switch connected in series between the first power supply and the second output terminal;
a first pull-down variable resistor and a third switch connected in series between a second power supply and the first output terminal;
a second pull-down variable resistor and a fourth switch connected in series between the second power supply and the second output terminal;
a floating variable resistor connected between the first output terminal and the second output terminal; and
coder logic to receive data bits and adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor responsive to the received data bits,
wherein the coder logic is further operable to vary a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor to maintain an effective output impedance for the line driver circuit that equals an impedance of a transmission line connected to the first output terminal and the second output terminal, and
wherein the coder logic is further operable to set the resistance of the first pull-up variable resistor and the second pull-up variable resistor to a value that is different from the resistance of the first pull-down variable resistor and the second pull-down variable resistor to generate a controlled common-mode voltage associated with the adjustable output voltage.
2. A line driver circuit including a first output terminal and a second output terminal, the line driver circuit comprising:
a first pull-up variable resistor and a first switch connected in series between a first power supply and the first output terminal;
a second pull-up variable resistor and a second switch connected in series between the first power supply and the second output terminal;
a first pull-down variable resistor and a third switch connected in series between a second power supply and the first output terminal;
a second pull-down variable resistor and a fourth switch connected in series between the second power supply and the second output terminal;
a floating variable resistor connected between the first output terminal and the second output terminal;
coder logic to receive data bits and adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor responsive to the received data bits; and
a voltage regulator to regulate a voltage of the first power supply to twice a maximum signal swing of the adjustable output voltage.
3. The line driver circuit of claim 2 , wherein the coder logic is further operable to vary a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor to maintain an effective output impedance for the line driver circuit that equals an impedance of a transmission line connected to the first output terminal and the second output terminal.
4. The line driver circuit of claim 2 , wherein the adjustable output voltage is adjustable from zero to the maximum signal swing.
5. The line driver circuit of claim 4 , wherein power consumption of the line driver circuit is directly proportional to the adjustable output voltage.
6. The line driver circuit of claim 5 , wherein a drive current associated with the line driver circuit is directly proportional to the adjustable output voltage.
7. The line driver circuit of claim 2 , wherein the coder logic is operable to digitally set the resistance of each of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor.
8. The line driver circuit of claim 2 , wherein the line driver circuit is a multi-level pulse amplitude modulation (PAM) line driver circuit.
9. The line driver of claim 8 , wherein the multi-level pulse amplitude modulation (PAM) line driver circuit is compliant with 100Base-T or 1000Base-T protocols.
10. A line driver circuit including a first output terminal and a second output terminal, the line driver circuit comprising:
a first switch connected between a first power supply and a first node;
a second switch connected between the first power supply and a second node;
a third switch connected between the first node and a second power supply;
a fourth switch connected between the second node and the second power supply;
a first variable resistor connected between the first node and the first output terminal;
a second variable resistor connected between the second node and the second output terminal;
a floating variable resistor connected between the first output terminal and the second output terminal;
coder logic to receive data bits and adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first variable resistor, and the second variable resistor responsive to the received data bits; and
a voltage regulator to regulate a voltage of the first power supply to twice a maximum signal swing of the adjustable output voltage.
11. The line driver circuit of claim 10 , wherein the coder logic is further operable to vary a resistance of one or more of the floating variable resistor, the first variable resistor, and the second variable resistor to maintain an effective output impedance for the line driver circuit that equals an impedance of a transmission line connected to the first output terminal and the second output terminal.
12. The line driver circuit of claim 10 , wherein the adjustable output voltage is adjustable from zero to the maximum signal swing.
13. The line driver circuit of claim 12 , wherein power consumption of the line driver circuit is directly proportional to the adjustable output voltage.
14. The line driver circuit of claim 13 , wherein a drive current associated with the line driver circuit is directly proportional to the adjustable output voltage.
15. The line driver circuit of claim 13 , wherein the coder logic is operable to digitally set the resistance of each of the floating variable resistor, the first variable resistor, and the second variable resistor.
16. The line driver circuit of claim 10 , wherein the line driver circuit is a multi-level pulse amplitude modulation (PAM) line driver circuit.
17. The line driver of claim 16 , wherein the multi-level pulse amplitude modulation (PAM) line driver circuit is compliant with 100Base-T or 1000Base-T protocols.