Semiconductor device having an interconnect that increases in impurity concentration as width increases
View Patent ↗The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.
1. A semiconductor device, comprising:
a plurality of interconnect layers;
wherein an interconnect in at least one interconnect layer among said plurality of interconnect layers contains an impurity; and
as a width of said interconnect in said at least one interconnect layer increases, a concentration of said impurity in said interconnect increases,
wherein said plurality of interconnect layers includes a lower interconnect layer including a shallow trench interconnect and an upper interconnect layer including a deep trench interconnect, said interconnect in said at least one interconnect layer among said plurality of interconnect layers is in said lower interconnect layer, and another interconnect in said upper interconnect layer is constituted of a metal that does not contain an impurity.
2. The semiconductor device according to claim 1 , wherein said interconnect in said at least one interconnect layer among said plurality of interconnect layers includes a wide interconnect having a thickness thinner than a width thereof, and a narrow interconnect having a thickness equal to or greater than a width thereof.
3. The semiconductor device according to claim 2 , wherein said wide interconnect contains said impurity in a concentration of 0.1 to 10 atomic %.
4. The semiconductor device according to claim 1 , wherein said interconnect in said at least one interconnect layer among said plurality of interconnect layers is 400 nm or less in thickness.
5. The semiconductor device according to claim 1 , wherein the interconnect in said at least one interconnect layer among said plurality of interconnect layers is predominantly composed of copper, and said impurity is an element having a lower standard electrode potential than copper.