Semiconductor device including a capacitance
View Patent ↗It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate ( 165 ), a buried oxide film ( 166 ) and an SOI layer ( 171 ), an isolating oxide film 167 ( 167 a to 167 c ) is selectively formed in an upper layer portion of the SOI layer ( 171 ) with a part of the SOI layer ( 171 ) remaining as a P − well region ( 169 ). Consequently, an isolation (partial isolation) structure is obtained. An N + diffusion region ( 168 ) is formed in the SOI layer ( 171 ) between the isolating oxide films ( 167 a ) and ( 167 b ) and a P + diffusion region ( 170 ) is formed in the SOI layer ( 171 ) between the isolating oxide films ( 167 b ) and ( 167 c ). Consequently, there is obtained a junction type variable capacitance (C 23 ) having a PN junction surface of the P − well region ( 169 ) provided under the isolating oxide film ( 167 b ) and the N + diffusion region ( 168 ).
1. A semiconductor device having a junction capacitance formed in an SOI layer of an SOI substrate constituted by a substrate, at least a surface of which is insulative, and said SOI layer of a first conductivity type provided on said surface of said substrate,
said junction capacitance including:
a first junction semiconductor region of a second conductivity type formed on said SOI layer;
a second junction semiconductor region of a first conductivity type formed on said SOI layer, said first and second junction semiconductor regions having a PN junction portion;
a first semiconductor region of the second conductivity type formed on said SOI layer;
a second semiconductor region of the first conductivity type formed on said SOI layer independently of said first semiconductor region; and
an isolating region provided in an upper layer portion of said SOI layer and serving to isolate said first and second semiconductor regions from each other, wherein
said isolating region includes a partial isolating region constituted by a partial insulating region provided in an upper layer portion of said SOI layer and an isolating semiconductor region of the first conductivity type which is a part of said SOI layer present in a lower layer portion,
said first junction semiconductor region includes said first semiconductor region,
said second junction semiconductor region includes said second semiconductor region and said isolating semiconductor region, and
said isolating semiconductor region has a PN junction portion together with said first semiconductor region.
2. A semiconductor device having a junction capacitance formed in an SOI layer of an SOI substrate constituted by a substrate, at least a surface of which is insulative, and said SOI layer of a first conductivity type provided on said surface of said substrate,
said junction capacitance including:
a first junction semiconductor region of a second conductivity type formed on said SOI layer;
a second junction semiconductor region of a first conductivity type formed on said SOI layer, said first and second junction semiconductor regions having a PN junction portion;
a body region for a capacitance of the first conductivity type formed in a surface of said SOI layer; and
first and second semiconductor regions of the second and first conductivity types formed to interpose therebetween said body region for a capacitance, said second semiconductor region having an impurity concentration to be set higher than that in said body region for a capacitance, wherein
said first junction semiconductor region includes said first semiconductor region,
said second junction semiconductor region includes said second semiconductor region and said body region for a capacitance, and
said first semiconductor region has a PN junction portion together with said body region for a capacitance.
3. The semiconductor device according to claim 2 , said junction capacitance further including:
a gate insulating film for a capacitance formed on said body region for a capacitance; and
a gate electrode for a capacitance formed on said gate insulating film for a capacitance.
4. The semiconductor device according to claim 2 , further comprising:
first and second silicide regions formed on surfaces of said first and second semiconductor regions.