Semiconductor testing device
View Patent ↗A semiconductor device has a bonding pad configured to be bonded to a bonding member, a test pad configured to contact with a test probe at a test, and an internal circuit electrically connected to the bonding pad and the test pad. The bonding pad overlaps with the internal circuit in a direction vertical to a surface of a semiconductor chip. The test pad does not overlap with the internal circuit in the direction.
1. A semiconductor device comprising:
a bonding pad coupled to an external electrode;
a test pad configured to contact with a test probe at a test; and
an internal circuit electrically connected to said bonding pad and said test pad,
wherein said bonding pad overlaps with said internal circuit in a direction vertical to a surface of a semiconductor chip, and said test pad does not overlap with said internal circuit in said direction,
wherein said bonding pad and said test pad are formed on a peripheral region of said semiconductor chip, and
wherein said test pad is located between said bonding pad and a nearest edge of said semiconductor chip.
2. A semiconductor device comprising:
a bonding pad configured to be bonded to a bonding member;
a test pad configured to contact with a test probe at a test;
a cover layer having separate apertures through which said bonding pad and said test pad are exposed, respectively; and
an internal circuit electrically connected to said bonding pad and said test pad,
wherein said bonding pad overlaps with said internal circuit in a direction vertical to a surface of a semiconductor chip, and said test pad does not overlap with said internal circuit in said direction,
wherein said bonding pad and said test pad are formed on a peripheral region of said semiconductor chip, and
wherein said test pad is located between said bonding pad and a nearest edge of said semiconductor chip.
3. The semiconductor device according to claim 1 , wherein said internal circuit is internal to said semiconductor chip.
4. The semiconductor device according to claim 1 , further comprising a conductive layer formed below said bonding pad and connected to said bonding pad via a through hole.
5. The semiconductor device according to claim 1 , further comprising a conductive layer formed below said test pad and connected to said test pad via a through hole.
6. The semiconductor device according to claim 1 , further comprising multi-layer interconnections electrically connected to said bonding pad and said test pad,
wherein said internal circuit includes a part of said multi-layer interconnections.
7. The semiconductor device according to claim 6 , further comprising a through hole connecting said multi-layer interconnections and located under an area between said bonding pad and said test pad.
8. The semiconductor device according to claim 6 , wherein at least one of said multi-layer interconnections is formed not to overlap with said bonding pad.
9. The semiconductor device according to claim 6 , wherein a number of interconnections of said multi-layer interconnections located under said bonding pad is smaller than a number of said multi-layer interconnections.
10. The semiconductor device according to claim 4 , through hole is formed in a reticular pattern.
11. The semiconductor device according to claim 5 , wherein said through hole has a wall shape.
12. The semiconductor device according to claim 1 , wherein said internal circuit includes a non-volatile memory.
13. A semiconductor device comprising:
a bonding pad coupled to an external electrode;
a test pad configured to contact with a test probe at a test; and
an internal circuit electrically connected to said bonding pad and said test pad,
wherein said internal circuit includes:
a first internal circuit which overlaps with said bonding pad in a direction vertical to a surface of a semiconductor chip; and
a second internal circuit which overlaps with said test pad in said direction,
wherein a distance between said test pad and said second internal circuit is larger than a distance between said bonding pad and said first internal circuit,
said bonding pad and said test pad are formed on a peripheral region of said semiconductor chip, and
said test pad is located between said bonding pad and a nearest edge of said semiconductor chip.
14. The semiconductor device according to claim 13 ,
further comprising a cover layer having separate apertures through which said bonding pad and said test pad are exposed, respectively.
15. The semiconductor device according to claim 13 , wherein said internal circuit is internal to said semiconductor chip.
16. The semiconductor device according to claim 13 , further comprising multi-layer interconnections electrically connected to said bonding pad and said test pad,
wherein said internal circuit includes a part of said multi-layer interconnections.
17. The semiconductor device according to claim 16 , further comprising a through hole connecting said multi-layer interconnections and located under an area between said bonding pad and said test pad.
18. The semiconductor device according to claim 16 , wherein at least one of said multi-layer interconnections is formed not to overlap with said bonding pad.