IP Library Granted Patent US 7,095,045
Granted Patent B2
US 7,095,045 · App. 10/998,182 · Granted Aug 22, 2006

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 7,095,045
App. No.
10/998,182
Granted
Aug 22, 2006
Kind
B2
Abstract

A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode.

Claims (38)

1. A semiconductor device comprising:

a substrate;

a pad electrode formed on said substrate; and

a bump electrode formed on said pad electrode,

wherein said pad electrode carries an irregular flaw, and

a pattern is provided between said pad electrode and said bump electrode so as to cover said irregular flaw.

2. The semiconductor device as claimed in claim 1 , wherein said pattern comprises an inorganic film.

3. The semiconductor device as claimed in claim 1 , wherein said pattern comprises an organic film.

4. The semiconductor device as claimed in claim 1 , wherein said pattern comprises a conductive film.

5. The semiconductor device as claimed in claim 1 , wherein said pattern comprises a laminated film combining an inorganic film or an organic film or a conductive film.

6. A manufacturing method of a semiconductor device, comprising the steps of:

forming a pad electrode on a substrate:;

conducting a test by contacting a probe needle to said pad electrode;

forming a pattern on a part of surface of said pad electrode so as to cover an irregularity formed by contact of said probe needle;

forming a conductive film on said surface of said pad electrode so as to cover said pattern;

forming a conductive foundation film on said pad electrode by an electrolytic plating process while using said conductive film as an electrode; and

forming a bump electrode on said conductive foundation film.

7. The manufacturing method of a semiconductor device as claimed in claim 6 , wherein said pattern is formed of an inorganic film of a silicon nitride film or a silicon oxide film.

8. The manufacturing method of a semiconductor device as claimed in claim 6 , wherein said pattern is formed of an inorganic film of a polyimide film.

9. The manufacturing method of a semiconductor device as claimed in claim 6 , wherein said pattern comprises a conductive film of Ag, Pt, Pd and Cu of a paste state.

10. A manufacturing method of a semiconductor device, comprising the steps of:

forming a pad electrode on a substrate;

conducting a test by contacting a probe needle to said pad electrode;

planarizing irregularity formed by contact of said probe needle;

forming a conductive film on a surface of said pad electrode so as to cover said planarized irregularity;

forming a conductive foundation film on said pad electrode by an electrolytic plating process while using said conductive film as an electrode; and

forming a bump electrode on said conductive foundation film.

11. The manufacturing method of a semiconductor device as claimed in claim 10 wherein said planarizing step comprises the step of dry etching said irregular flaw.

12. The manufacturing method of a semiconductor device as claimed in claim 10 , wherein said planarizing step comprises the step of wet etching said irregular flaw.

13. The manufacturing method of a semiconductor device as claimed in claim 10 , wherein said planarizing step comprises the step of fusing said pad electrode at 600–800 □.

14. The manufacturing method of a semiconductor device wherein said polarizing step comprises the step of applying a pressure mechanically to said irregular flaw.

15. A manufacturing method of a semiconductor device, comprising the steps of:

forming a pad electrode on a substrate;

conducting a test by contacting a probe needle to said pad electrode;

forming an electrode film on a front surface of said pad electrode so as to cover an irregularity formed by contact of said probe needle;

forming a conductive foundation film on said pad electrode by an electrolytic plating process while using said electrode film as an electrode; and

forming a bump electrode an said conductive foundation film,

wherein said electrode film has a thickness exceeding a step height caused by said irregularity.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0337 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2005
From: CHIBA, SHUICHI; ISHIGURI, MASAHIKO; MURATA, KOICHI; WATANABE, EIJI; TAMAGAWA, MICHIAKI; SATOH, AKIRA; TOIDA, YASUSHI; MISAWA, KAZUHIRO
To: FUJITSU LIMITED
Reel/Frame 016371/0805 →