Design method and architecture for power gate switch placement
View Patent ↗A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells.
1. A method for placing power gate cells in a physical circuit design of an integrated circuit, comprising:
in the physical design of the integrated circuit stored in a computer system:
providing a conductor for carrying a voltage reference;
placing a plurality of logic cells in one or more rows, wherein the logic cells include a first collection of the logic cells each having a terminal for coupling a virtual voltage reference; and
placing a plurality of power gate cells into unoccupied spaces remaining after placing the logic cells in the one or more rows, each power gate cell having a terminal for coupling the virtual voltage reference and a terminal for coupling to the conductor for carrying the voltage reference.
2. A method as in claim 1 , wherein the first collection of logic cells are placed contiguously and wherein one of the power gate cells is placed abutting one of the logic cells in the first collection of logic cells.
3. A method as in claim 1 , wherein conductors at a predetermined position are provided in abutting logic cell and the power gate cell, such that the terminal for coupling the virtual voltage reference in the logic cell is connected to the terminals for coupling the virtual voltage reference of the power gate cell by virtue of the placement.
4. A method as in claim 1 , wherein the voltage reference is a ground voltage reference.
5. A method as in claim 1 , wherein the voltage reference is a power supply voltage reference.
6. A method as in claim 1 , wherein the plurality of the power gate cells are placed in unoccupied spaces between the logic cells that result from placing of the logic cells, the logic cells being placed using an algorithm that provides an initial placement of the logic cells without taking into account subsequent placements of the power gate cells.
7. A method as in claim 1 , wherein a size of each power gate cell placed in the unoccupied spaces is computed according to an estimate of currents in the logic cells to be connected to the power gate cell.
8. A method as in claim 7 , wherein the estimate of the currents is carried out using a static estimation technique.
9. A method as in claim 7 , wherein the estimate of the currents is carried out using a dynamic estimation technique.
10. A method as in claim 1 , wherein a size of each power gate cell placed in the unoccupied spaces is computed using a number of transistors in the logic cells to which that power gate cell is connected.
11. A method as in claim 1 , further comprising routing the virtual voltage reference to connect the terminals for coupling the virtual voltage reference of the first collection of the logic cells to the terminals for coupling the virtual voltage reference of the power gate cells.
12. A method as in claim 11 , wherein the routing is carried out using conductors in routing channels.
13. A method as in claim 11 , wherein the routing is carried out using a channel-less routing technique.
14. A method as in claim 11 , wherein the routing is carried out using a shared virtual voltage reference bus.
15. A method as in claim 1 , further comprising resizing the unoccupied spaces by moving the logic cells within each row along a lateral direction.
16. A method as in claim 1 , further comprising resizing the unoccupied spaces by moving the logic cells across rows.
17. A method as in claim 1 , wherein, prior to placing the power gate cells, a placement optimization step is performed to rearrange the logic cells to achieve a specified distribution of the unoccupied space.
18. A method as in claim 17 , wherein the specified distribution is achieved by targeting a specified distance along each row between two power gate cells.
19. A method as in claim 1 , further comprising connecting a second collection of logic cells directly to the conductor for providing the voltage reference.
20. A method as in claim 1 , wherein widths of conductors used for connecting between the logic cells and the power gate cells are provided according to an estimate of wire resistance.
21. A method as in claim 1 , wherein the logic cells having a common sleep domain are placed in close proximity of each other.
22. A method as in claim 21 , further comprising traversing a netlist to identify a control signal of the power gate associated with each logic cell.
23. A method as in claim 22 , wherein the traversing comprises backward tracing the control signal through buffers and inverter pairs.
24. A method as in claim 1 , wherein the logic cells and the power gate cells are placed according to a constraint relating to a user designated distance.
25. A method as in claim 1 , wherein the logic cells and the power gate cells are placed according to a constraint relating to an estimated voltage drop.
26. A method as in claim 1 , wherein the logic cells and the power gate cells are placed according to a constraint relating to signal integrity concerns.
27. A method as in claim 1 , wherein each power gate cell is placed according to a global route model which estimates a wire resistance based on the placement of the power gate cell and the placements of the logic cell associated with the power gate.
28. A method as in claim 1 , wherein each power gate cell is placed according to a global route model which estimates a current based on the placement of the power gate cell and the placements of the logic cell associated with the power gate.
29. A method as in claim 1 , wherein the power gate cells are assigned to logic cells according to a descending order of the current requirements.
30. A method as in claim 1 , wherein the power gate cell is placed subject to a current limit constraint.
31. A method as in claim 1 , wherein the logic cells using a first placement step and the power gate cells are placed using a second placement steps, wherein the first placement step is performed without regard to the placement of the power gate cells.
32. A method as in claim 1 , wherein the logic cells and the power gate cells are placed using multiple placement steps, wherein one of the placement steps is carried out with the power gate cells excluded.
33. A method as in claim 32 , further comprising assigning the power gate cells a high cost function, so as to exclude the power gate cells in that placement step.
34. A method as in claim 32 , wherein the power gate cells are excluded from a library used in that placement step.