Patent Assignment
Reel/Frame 022416/0026
Security Agreement
Recorded: 2009-03-18
Pages: 13
Assignor
SEQUENCE DESIGN, INC.
Executed: 2009-02-11
Assignee
FOCUS VENTURES II, LP
525 UNIVERSITY AVE., #1400, PALO ALTO, CALIFORNIA, 94301
Covered Properties
(31)
A System and Method for Extracting Parasitic Impedance from an Integrated Circuit Layout
Patent:
5,901,063 →
Application:
08/804,524 →
Methods for Determining on-Chip Interconnect Process Parameters
Patent:
6,057,171 →
Application:
08/937,393 →
Methods for Determining on-Chip Interconnect Process Parameters
Patent:
6,291,254 →
Application:
09/244,616 →
Methods for Determining on-Chip Interconnect Process Parameters
Patent:
6,312,963 →
Application:
09/245,812 →
Method and System for Extraction of Parasitic Interconnect Impedance Including Inductance
Patent:
6,381,730 →
Application:
09/350,966 →
Method for Determining on-Chip Sheet Resistivity
Patent:
6,403,389 →
Application:
09/373,923 →
Method and Apparatus for Logic Synthesis (Inferring Complex Components)
Patent:
6,493,648 →
Application:
09/375,254 →
Method and Apparatus for Logic Synthesis (Word Oriented Netlist)
Patent:
6,574,787 →
Application:
09/375,836 →
Method and Apparatus for Logic Synthesis with Elaboration
Patent:
6,519,755 →
Application:
09/375,843 →
Method for Modeling a Conductive Semiconductor Substrate
Patent:
6,311,312 →
Application:
09/405,510 →
Method and Apparatus for Interconnect-Driven Optimization of Integrated Circuit Design
Patent:
6,591,407 →
Application:
09/516,489 →
Rtl Power Analysis Using Gate-Level Cell Power Models
Patent:
6,598,209 →
Application:
09/798,016 →
Circuit Optimization for Minimum Path Timing Violations
Patent:
6,701,505 →
Application:
10/008,458 →
Method for Match Delay Buffer Insertion
Patent:
6,701,506 →
Application:
10/022,743 →
Method for Optimal Driver Selection
Patent:
6,754,877 →
Application:
10/022,747 →
Method for Determining a Zero-Skew Buffer Insertion Point
Patent:
6,701,507 →
Application:
10/022,751 →
Method for Balanced-Delay Clock Tree Insertion
Patent:
6,698,006 →
Application:
10/023,329 →
Method and System for Extraction of Parasitic Interconnect Impedance Including Inductance
Vectorless Instantaneous Current Estimation
Patent:
6,807,660 →
Application:
10/262,914 →
Method and Apparatus for Interconnect-Driven Optimization of Integrated Circuit Design
Rtl Power Analysis Using Gate-Level Cell Power Models
Circuit Optimization for Minimum Path Timing Violations
Current Scheduling System and Method for Optimizing Multi-Threshold Cmos Designs
Method for Optimal Driver Selection
Vectorless Instantaneous Current Estimation
Design Method and Architecture for Power Gate Switch Placement
Method That Allows Flexible Evaluation of Power-Gated Circuits
Automatic Extension of Clock Gating Technique to Fine-Grained Power Gating
Design Method and Architecture for Power Gate Switch Placement and Interconnection Using Tapless Libraries
Automatic Voltage Drop Optimization
Automatic Extension of Clock Gating Technique to Fine-Grained Power Gating
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
ACQUISIT8ION of 100% Interest
Aug 25, 2001
From: SAPPHIRE DESIGN AUTOMATION, INC.
To: SEQUENCE DESIGN, INC.
Reel/Frame 012117/0205 →
Assignment of Assignor's Interest
Dec 14, 2001
From: SRINIVASAN, ADI; ALLEN, DAVID L.
To: SEQUENCE DESIGN, INC.
Reel/Frame 012408/0842 →
Assignment of Assignor's Interest
Dec 14, 2001
From: SRINIVASAN, ADI
To: SEQUENCE DESIGN, INC.
Reel/Frame 012396/0161 →
Assignment of Assignor's Interest
Dec 14, 2001
From: SRINIVASAN, ADI; ALLEN, DAVID L.
To: SEQUENCE DESIGN, INC.
Reel/Frame 012396/0086 →
Assignment of Assignor's Interest
Dec 14, 2001
From: SRINIVASAN, ADI
To: SEQUENCE DESIGN, INC.
Reel/Frame 012396/0156 →
Assignment of Assignor's Interest
Dec 17, 2003
From: FRENKIL, GERALD L.
To: SEQUENCE DESIGN, INC.
Reel/Frame 014832/0248 →
Security Agreement
Dec 23, 2004
From: SEQUENCE DESIGN, INC.
To: SILICON VALLEY BANK
Reel/Frame 016087/0906 →
Intellectual Property Security Agreement
Jul 6, 2008
From: SEQUENCE DESIGN, INC.
To: FOCUS VENTURES II, LP
Reel/Frame 021194/0156 →
Security Agreement
Jul 8, 2008
From: SEQUENCE DESIGN, INC.
To: SILICON VALLEY BANK
Reel/Frame 021205/0667 →
Release of Security Interest
Sep 9, 2009
From: FOCUS VENTURES II, LP
To: SEQUENCE DESIGN, INC.
Reel/Frame 023196/0907 →
Release of Security Interest
Sep 9, 2009
From: FOCUS VENTURES II, LP
To: SEQUENCE DESIGN, INC.
Reel/Frame 023196/0932 →
Release
Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023263/0476 →
Release
Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023273/0447 →
Release
Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023263/0489 →
Release
Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023263/0480 →
Assignment of Assignor's Interest
Mar 24, 2011
From: SEQUENCE DESIGN, INC.
To: APACHE DESIGN SOLUTIONS, INC.
Reel/Frame 026015/0111 →
Change of Name
Jan 9, 2012
From: APACHE DESIGN SOLUTIONS, INC.
To: APACHE DESIGN, INC.
Reel/Frame 027500/0127 →
Merger
Sep 2, 2020
From: APACHE DESIGN, INC.
To: ANSYS, INC.
Reel/Frame 053674/0176 →