Automatic extension of clock gating technique to fine-grained power gating
View Patent ↗A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.
1. A method for power gating, comprising:
identifying one or more registers being clocked by a gated clock signal derived from a combination of a clock signal and an enable signal;
identifying a logic circuit in an output logic cone of the output signals of the one or more registers;
providing a switch cell to be connected between the logic circuits and a voltage reference, and
controlling the switch cell using a sleep signal derived from the enable signals, wherein a signal path couples the enable signal to the sleep signal such that the sleep signal is deasserted within a predetermined delay when the enable signal is asserted.
2. A method as in claim 1 , wherein the enable signal is provided as the sleep signal to the logic circuit through a latch.
3. A method as in claim 2 , wherein gated clock signal is an output signal of an integrated clock-gating cell, and wherein the enable signal is provided as the sleep signal to the logic circuits through a latch.
4. A method as in claim 2 , wherein the latch is a part of the integrated clock-gating cell.
5. A method as in claim 1 , wherein the voltage reference is a ground voltage reference.
6. A method as in claim 1 , wherein the gated clock signal is an output signal of an integrated clock-gating cell.
7. A method as in claim 1 , further comprising retaining in a holder cell the output signals of the logic circuit during a time period in which the sleep signal is asserted.
8. A method as in claim 1 , wherein the enable signal is provided to the logic circuit through a first latch and a second latch, wherein the first latch and the second latch transfer a logic value from their input terminals to their output terminals at different logic levels of the clock signal.
9. A method as in claim 1 , wherein the enable signal is provided to the logic circuit through a flip-flop.
10. A method as in claim 1 , wherein the signal path comprises an OR gate that gates the enable signal with a signal derived from the gated clock signal.
11. A circuit for power gating a logic circuit within an output logic cone of one or more registers, comprising:
a switch circuit connecting the logic circuit to a voltage reference, the switch cell being controlled by a sleep signal; and
a clock-gating circuit receiving an enable signal and a clock signal, the clock-gating circuit deriving both a gated clock signal to clock the registers and the sleep signal based on the enable signal, wherein a signal path couples the enable signal to the sleep signal such that the sleep signal is deasserted within a predetermined delay when the enable signal is asserted.
12. A circuit as in claim 11 , wherein the clock-gating circuit provides the enable as the sleep signal through a latch.
13. A circuit as in claim 12 , wherein the clock-gating circuit comprises an integrated clock-gating cell that outputs the gated clock signal, and a latch that outputs the enable signal as the sleep signal.
14. A circuit as in claim 12 , wherein the latch is a part of the integrated clock-gating cell.
15. A circuit as in claim 11 , wherein the voltage reference is a ground voltage reference.
16. A circuit as in claim 11 , wherein the gated clock signal is an output signal of an integrated clock-gating cell.
17. A circuit as in claim 11 , further comprising a holder cell that retains the output signals of the logic circuit during a time period in which the sleep signal is asserted.
18. A circuit as in claim 11 , wherein the enable signal is provided to the logic circuit through a first latch and a second latch, wherein the first latch and the second latch transfer a logic value from their input terminals to their output terminals at different logic levels of the clock signal.
19. A circuit as in claim 11 , wherein the enable signal is provided to the logic circuit through a flip-flop.
20. A circuit as in claim 11 , wherein the signal path comprises an OR gate that gates the enable signal with a signal derived from the gated clock signal.