IP Library › Assignment 016087/0906
Patent Assignment
Reel/Frame 016087/0906

Security Agreement

Recorded: 2004-12-23 Pages: 11
Assignor
SEQUENCE DESIGN, INC.
Executed: 2004-11-24
Assignee
SILICON VALLEY BANK
3003 TASMAN DR., SANTA CLARA, CALIFORNIA, 95054
Covered Properties (20)
A System and Method for Extracting Parasitic Impedance from an Integrated Circuit Layout
Patent: 5,901,063 →
Application: 08/804,524 →
Methods for Determining on-Chip Interconnect Process Parameters
Patent: 6,057,171 →
Application: 08/937,393 →
Methods for Determining on-Chip Interconnect Process Parameters
Patent: 6,312,963 →
Application: 09/245,812 →
Method for Determining on-Chip Sheet Resistivity
Patent: 6,403,389 →
Application: 09/373,923 →
Method and Apparatus for Logic Synthesis (Inferring Complex Components)
Patent: 6,493,648 →
Application: 09/375,254 →
Method and Apparatus for Logic Synthesis (Word Oriented Netlist)
Patent: 6,574,787 →
Application: 09/375,836 →
Method and Apparatus for Interconnect-Driven Optimization of Integrated Circuit Design
Patent: 6,591,407 →
Application: 09/516,489 →
Rtl Power Analysis Using Gate-Level Cell Power Models
Patent: 6,598,209 →
Application: 09/798,016 →
Circuit Optimization for Minimum Path Timing Violations
Patent: 6,701,505 →
Application: 10/008,458 →
Method for Match Delay Buffer Insertion
Patent: 6,701,506 →
Application: 10/022,743 →
Method for Optimal Driver Selection
Patent: 6,754,877 →
Application: 10/022,747 →
Method for Determining a Zero-Skew Buffer Insertion Point
Patent: 6,701,507 →
Application: 10/022,751 →
Method for Balanced-Delay Clock Tree Insertion
Patent: 6,698,006 →
Application: 10/023,329 →
Method and System for Extraction of Parasitic Interconnect Impedance Including Inductance
Patent: 6,643,831 →
Application: 10/057,165 →
Publication: US 2002/0104063
Vectorless Instantaneous Current Estimation
Patent: 6,807,660 →
Application: 10/262,914 →
Method and Apparatus for Interconnect-Driven Optimization of Integrated Circuit Design
Patent: 7,222,311 →
Application: 10/387,644 →
Publication: US 2003/0177455
Rtl Power Analysis Using Gate-Level Cell Power Models
Patent: 6,901,565 →
Application: 10/447,076 →
Publication: US 2003/0208733
Circuit Optimization for Minimum Path Timing Violations
Patent: 7,222,318 →
Application: 10/627,933 →
Publication: US 2004/0088664
Current Scheduling System and Method for Optimizing Multi-Threshold Cmos Designs
Patent: 7,117,457 →
Application: 10/739,659 →
Publication: US 2005/0138588
Vectorless Instantaneous Current Estimation
Patent: 7,185,300 →
Application: 10/926,660 →
Publication: US 2005/0028119
Related Assignments (18)
Other recorded transfers of the patents in this record — the chain of ownership.
ACQUISIT8ION of 100% Interest Aug 25, 2001
From: SAPPHIRE DESIGN AUTOMATION, INC.
To: SEQUENCE DESIGN, INC.
Reel/Frame 012117/0205 →
Assignment of Assignor's Interest Dec 14, 2001
From: SRINIVASAN, ADI; ALLEN, DAVID L.
To: SEQUENCE DESIGN, INC.
Reel/Frame 012396/0086 →
Assignment of Assignor's Interest Dec 14, 2001
From: SRINIVASAN, ADI
To: SEQUENCE DESIGN, INC.
Reel/Frame 012396/0156 →
Assignment of Assignor's Interest Dec 14, 2001
From: SRINIVASAN, ADI; ALLEN, DAVID L.
To: SEQUENCE DESIGN, INC.
Reel/Frame 012408/0842 →
Assignment of Assignor's Interest Dec 14, 2001
From: SRINIVASAN, ADI
To: SEQUENCE DESIGN, INC.
Reel/Frame 012396/0161 →
Assignment of Assignor's Interest Dec 17, 2003
From: FRENKIL, GERALD L.
To: SEQUENCE DESIGN, INC.
Reel/Frame 014832/0248 →
Intellectual Property Security Agreement Jul 6, 2008
From: SEQUENCE DESIGN, INC.
To: FOCUS VENTURES II, LP
Reel/Frame 021194/0156 →
Security Agreement Jul 8, 2008
From: SEQUENCE DESIGN, INC.
To: SILICON VALLEY BANK
Reel/Frame 021205/0667 →
Security Agreement Mar 18, 2009
From: SEQUENCE DESIGN, INC.
To: FOCUS VENTURES II, LP
Reel/Frame 022416/0026 →
Release of Security Interest Sep 9, 2009
From: FOCUS VENTURES II, LP
To: SEQUENCE DESIGN, INC.
Reel/Frame 023196/0932 →
Release of Security Interest Sep 9, 2009
From: FOCUS VENTURES II, LP
To: SEQUENCE DESIGN, INC.
Reel/Frame 023196/0907 →
Release Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023273/0447 →
Release Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023263/0476 →
Release Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023263/0480 →
Release Sep 22, 2009
From: SILICON VALLEY BANK
To: SEQUENCE DESIGN, INC.
Reel/Frame 023263/0489 →
Assignment of Assignor's Interest Mar 24, 2011
From: SEQUENCE DESIGN, INC.
To: APACHE DESIGN SOLUTIONS, INC.
Reel/Frame 026015/0111 →
Change of Name Jan 9, 2012
From: APACHE DESIGN SOLUTIONS, INC.
To: APACHE DESIGN, INC.
Reel/Frame 027500/0127 →
Merger Sep 2, 2020
From: APACHE DESIGN, INC.
To: ANSYS, INC.
Reel/Frame 053674/0176 →