Vectorless instantaneous current estimation
View Patent ↗A current waveform for an electronic circuit is calculated from a description of the circuit at a given level of abstraction without requiring a detailed simulation. In one embodiment, the waveform is estimated without using test vectors, and uses an analysis time step or “granularity” that is much shorter than a clock cycle. The method is applicable for calculating worst-case instantaneous current.
1. A method for accurately calculating a current waveform of a circuit having one or more clock networks, multiple register elements and multiple logic elements, using a circuit description of the circuit, comprising:
performing an analysis of the circuit, the analysis relating switching characteristics of the register elements with transitions in the clock signals of the clock networks and comprising;
(a) initially classifying each register element in the circuit as responding to a selected transition in a selected one of the clock networks; and
(b) reclassifying each register element according to a circuit configuration associated with the register elements; and
constructing current waveforms based on the switching characteristics of the register elements and the logic elements relative to transitions in the clock signals.
2. A method as in claim 1 , further comprising performing a static timing analysis of the circuit.
3. A method as in claim 1 , wherein the analysis traverses from a root node in the clock networks.
4. A method as in claim 1 , wherein the analysis comprises:
expressing the circuit as a levelized netlist; and
traversing the levelized netlist from a lowest level register.
5. A method as in claim 1 , wherein the analysis comprises:
selecting a group of related circuit elements; and
traversing the circuit downstream from each circuit element in the group of related circuit elements.
6. A method as in claim 5 , wherein the related circuit elements are placed proximately to each other.
7. A method as in claim 1 , wherein the circuit configuration comprises the relationship between the register element and one or more register elements that provide input signals to the register element.
8. A method as in claim 7 , wherein the relationship comprises a logic inversion path.
9. A method as in claim 1 , wherein the circuit configuration comprises a recirculating path associated with a data input terminal of the register.
10. A method as in claim 1 , wherein the circuit configuration comprises a gating element in a clock network associated with the register element.
11. A method as in claim 1 , wherein the analysis comprises classifying a combinational logic element based on one or more states of input signals to the combinational logic element.
12. A method as in claim 1 , wherein constructing waveform comprises scheduling a switching event for each circuit element.
13. A method as in claim 1 , wherein constructing the waveform comprises:
creating an individual current waveform for each clock network and aligning and aggregating the individual current waveforms.
14. A method as in claim 13 , wherein the clock networks are asynchronous to each other.
15. A method as in claim 1 , wherein the current waveform comprises a reasonable worst-case instantaneous current waveform.
16. A method as in claim 1 , further comprising specifying an initial state of the circuit based on an analysis of the circuit description.
17. A method as in claim 1 , further comprising specifying an initial state of the circuit based upon a placement of the circuit elements.
18. A method as in claim 1 , further comprising specifying a user-defined initial state for the circuit.
19. A method as in claim 18 , wherein the user-defined initial state includes a scan vector.
20. A method as in claim 1 , further comprising introducing a skew in one of the clock networks to modify the current waveform.
21. A method as in claim 1 , further comprising specifying an exclusion break point for a circuit element.
22. A method as in claim 1 , further comprising specifying states of control signals in the circuit.
23. A method as in claim 22 , wherein the control signals comprise internal control signals.
24. A method as in claim 23 , wherein the control signals comprise input and output control signals.
25. A method as in claim 1 , further comprising providing as output a current model suitable for use in a circuit simulation tool.
26. A method as in claim 1 , wherein the current waveform represents current flowing from a power supply source.
27. A method as in claim 1 , wherein the current waveform represents current flowing into a ground reference current sink.
28. The method of claim 1 , modifying the circuit based on an analysis of the current waveforms.
29. The method of claim 28 , wherein the modifying comprises introducing clock skews to reduce one or more peak values of the current waveforms.