Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition
View Patent ↗A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is then etched using an acidic solution. Lastly, a conductive layer is formed on an exposed surface of the etched conductive interconnect.
1. A method of forming an integrated circuit, the method comprising:
forming a dielectric layer on a semiconductor wafer;
forming a trench in the dielectric layer;
forming a conductive interconnect within the trench, wherein the conductive interconnect comprises copper;
etching the conductive interconnect using an acidic solution;
simultaneously applying an electroless plating solution and a slurry to the exposed surface of the etched conductive interconnect and an exposed surface of the dielectric layer.
2. The method of claim 1 further comprising polishing the exposed surface of the dielectric layer as the electroless plating solution and the slurry is applied thereto.
3. The method of claim 2 wherein a conductive layer formed on the exposed surface of the etched conductive interconnect remains after polishing the exposed surface of the dielectric.
4. The method of claim 1 further comprising:
passing the electroless plating solution from a first reservoir to the exposed surface of the etched conductive layer and the exposed surface of the dielectric;
passing the slurry from a second reservoir to the exposed surface of the etched conductive layer and the exposed surface of the dielectric.
5. The method of claim 1 further comprising forming a conductive layer on an exposed surface of the etched conductive interconnect, wherein forming the conductive layer comprises the act of applying the electroless plating solution and the slurry to the exposed surface of the etched conductive interconnect and the exposed surface of the dielectric layer.
6. A method comprising:
forming a dielectric layer on a semiconductor wafer;
forming a trench in the dielectric layer;
forming a conductive interconnect within the trench, wherein the conductive interconnect comprises copper;
forming a conductive layer on an exposed surface of the conductive interconnect;
removing conductive material deposited on an exposed surface of the dielectric;
wherein the conductive layer is formed on the exposed surface of the conductive interconnect while conductive material is removed from the exposed surface of the dielectric by simultaneously applying an electroless plating solution and a slurry to the exposed surface of the conductive interconnect and an exposed surface of the dielectric layer.
7. The method of claim 6 wherein the act of removing conductive material comprises polishing the exposed surface of the dielectric using a CMP tool.
8. The method of claim 6 further comprising an act of etching the conductive interconnect using an acid solution, wherein the act of etching occurs before formation of the conductive layer.
9. The method of claim 8 further comprising:
attaching the semiconductor wafer to a wafer carrier of a CMP tool;
detaching the semiconductor wafer from the wafer carrier;
wherein the conductive layer is formed on the exposed surface of the conductive interconnect after attaching the semiconductor wafer to the wafer carrier but before detaching the semiconductor wafer from the wafer carrier;
wherein the conductive material is removed from the exposed surface of the dielectric after attaching the semiconductor wafer to the wafer carrier but before detaching the semiconductor wafer from the wafer carrier;
wherein the conductive interconnect is etched after attaching the semiconductor wafer to the wafer carrier but before detaching the semiconductor wafer from the wafer carrier.