Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate, at opposite ends of the pre-active pattern. The interchannel layers are then selectively removed, to form tunnels passing through the pre-active pattern, thereby defining an active channel pattern including the tunnels and channels including the channel layers. The channels are doped with phosphorus after selectively removing the interchannel layers. A gate electrode is then formed in the tunnels and surrounding the channels.
1. A method of manufacturing an integrated circuit field effect transistor comprising:
forming a pre-active pattern on a surface of a substrate while refraining from doping the pre-active pattern with phosphorous, the pre-active pattern comprising a series of interchannel layers and channel layers stacked alternately upon each other;
forming source/drain regions on the substrate, at opposite ends of the pre-active pattern;
selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the pre-active pattern, thereby defining an active channel pattern comprising the tunnels and a plurality of channels comprising the channel layers;
doping the channels with phosphorous after selectively removing the plurality of interchannel layers; and
forming a gate electrode in the tunnels and surrounding the channels;
wherein the channel layers comprise single crystalline silicon and wherein the interchannel layers comprise single crystalline silicon-germanium.
2. The method as claimed in claim 1 wherein the integrated circuit field effect transistor is a P-channel integrated circuit field effect transistor.
3. The method according to claim 1 wherein selectively removing is performed using poly etchant.
4. The method according to claim 1 wherein doping the channels is performed using ion implantation.
5. The method according to claim 1 wherein doping the channels is performed using plasma doping.
6. The method as claimed in claim 1 wherein the forming a gate electrode comprises forming a gate electrode to fill up the tunnels and surround the channels.
7. The method as claimed in claim 1 , wherein the substrate comprises silicon, silicon-germanium, silicon-on-insulator (SOI) and/or silicon-germanium-on-insulator (SGOI).
8. The method as claimed in claim 1 , wherein selectively removing is performed using an isotropic etching process.
9. A method of manufacturing integrated circuit N-channel and P-channel field effect transistors comprising:
forming an N-channel pre-active pattern and a P-channel pre-active pattern on a surface of a substrate, while refraining from doping the N-channel and P-channel pre-active patterns with phosphorous, the respective N-channel and P-channel pre-active patterns comprising a series of interchannel layers and respective N-channel layers and P-channel layers stacked alternately upon each other;
forming source/drain regions on the substrate, at opposite ends of each of the N-channel and P-channel pre-active patterns;
selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the N-channel and P-channel pre-active patterns, thereby defining respective active N-channel and P-channel patterns comprising the tunnels and a plurality of respective N-channels and P-channels comprising the channel layers;
doping the P-channels of the active P-channel patterns with phosphorous after selectively removing the plurality of interchannel layers, while refraining from doping the N-channels of the active N-channel patterns with phosphorous after selectively removing the plurality of interchannel layers; and
forming a gate electrode in the tunnels and surrounding the N-channels and the P-channels;
wherein the following is performed after selectively removing the plurality of interchannel layers;
doping the N-channels of the active N-channel patterns with boron, while refraining from doping the P-channels of the active P-channel patterns with boron.
10. A method of manufacturing integrated circuit N-channel and P-channel field effect transistors comprising:
forming an N-channel pre-active pattern and a P-channel pre-active pattern on a surface of a substrate, while refraining from doping the N-channel and P-channel pre-active patterns with phosphorous, the respective N-channel and P-channel pre-active patterns comprising a series of interchannel layers and respective N-channel layers and P-channel layers stacked alternately upon each other:
forming source/drain regions on the substrate, at opposite ends of each of the N-channel and P-channel pre-active patterns;
selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the N-channel and P-channel pre-active patterns, thereby defining respective active N-channel and P-channel patterns comprising the tunnels and a plurality of respective N-channels and P-channels comprising the channel layers;
doping the P-channels of the active P-channel patterns with phosphorous after selectively removing the plurality of interchannel layers, while refraining from doping the N-channels of the active N-channel patterns with phosphorous after selectively removing the plurality of interchannel layers; and
forming a gate electrode in the tunnels and surrounding the N-channels and the P-channels;
wherein the following is performed before selectively removing the plurality of interchannel layers:
doping the N-channel layers of the N-channel pre-active patterns with boron, while refraining from doping the P-channel layers of the P-channel pre-active patterns with boron.
11. A method of manufacturing integrated circuit N-channel and P-channel field effect transistors comprising:
forming an N-channel pre-active pattern and a P-channel pre-active pattern on a surface of a substrate, while refraining from doping the N-channel and P-channel pre-active patterns with phosphorous, the respective N-channel and P-channel pre-active patterns comprising a series of interchannel layers and respective N-channel layers and P-channel layers stacked alternately upon each other;
forming source/drain regions on the substrate, at opposite ends of each of the N-channel and P-channel pre-active patterns:
selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the N-channel and P-channel pre-active patterns, thereby defining respective active N-channel and P-channel patterns comprising the tunnels and a plurality of respective N-channels and P-channels comprising the channel layers;
doping the P-channels of the active P-channel patterns with phosphorous after selectively removing the plurality of interchannel layers, while refraining from doping the N-channels of the active N-channel patterns with phosphorous after selectively removing the plurality of interchannel layers; and
forming a gate electrode in the tunnels and surrounding the N-channels and the P-channels;
wherein the following is performed after selectively removing the plurality of interchannel layers:
doping the N-channels of the active N-channel patterns and the P-channels of the active P-channel patterns with boron.
12. A method of manufacturing integrated circuit N-channel and P-channel field effect transistors comprising:
forming an N-channel pre-active pattern and a P-channel pre-active pattern on a surface of a substrate, while refraining from doping the N-channel and P-channel pre-active patterns with phosphorous, the respective N-channel and P-channel pre-active patterns comprising a series of interchannel layers and respective N-channel layers and P-channel layers stacked alternately upon each other;
forming source/drain regions on the substrate, at opposite ends of each of the N-channel and P-channel pre-active patterns;
selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the N-channel and P-channel pre-active patterns, thereby defining respective active N-channel and P-channel patterns comprising the tunnels and a plurality of respective N-channels and P-channels comprising the channel layers;
doping the P-channels of the active P-channel patterns with phosphorous after selectively removing the plurality of interchannel layers, while refraining from doping the N-channels of the active N-channel patterns with phosphorous after selectively removing the plurality of interchannel layers; and
forming a gate electrode in the tunnels and surrounding the N-channels and the P-channels;
wherein the following is performed before selectively removing the plurality of interchannel layers:
doping the N-channel layers of the active N-channel pre-active patterns and the P-channel layers of the P-channel pre-active patterns with boron.
13. A method of manufacturing integrated circuit N-channel and P-channel field effect transistors comprising:
forming an N-channel pre-active pattern and a P-channel pre-active pattern on a surface of a substrate, while refraining from doping the N-channel and P-channel pre-active patterns with phosphorous, the respective N-channel and P-channel pre-active patterns comprising a series of interchannel layers and respective N-channel layers and P-channel layers stacked alternately upon each other;
forming source/drain regions on the substrate, at opposite ends of each of the N-channel and P-channel pre-active patterns;
selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the N-channel and P-channel pre-active patterns, thereby defining respective active N-channel and P-channel patterns comprising the tunnels and a plurality of respective N-channels and P-channels comprising the channel layers;
doping the P-channels of the active P-channel patterns with phosphorous after selectively removing the plurality of interchannel layers, while refraining from doping the N-channels of the active N-channel patterns with phosphorous after selectively removing the plurality of interchannel layers; and
forming a gate electrode in the tunnels and surrounding the N-channels and the P-channels;
wherein the channel layers comprise single crystalline silicon and wherein the interchannel layers comprises single crystalline silicon-germanium.
14. The method according to claim 13 wherein selectively removing is performed using poly etchant.
15. The method according to claim 13 wherein doping the P-channels is performed using ion implantation.
16. The method according to claim 13 wherein doping the P-channels is performed using plasma doping.
17. The method as claimed in claim 13 wherein the forming a gate electrode comprises forming a gate electrode to fill up the tunnels and surround the N-channels and the P-channels.
18. The method as claimed in claim 13 , wherein the substrate comprises silicon, silicon-germanium, silicon-on-insulator (SOI) and/or silicon-germanium-on-insulator (SGOI).
19. The method according to claim 13 wherein selectively removing is performed using an isotropic etching process.