Cache memory and method to maintain cache-coherence between cache memory units

1. A cache memory that passes data to a processor based on a request from the processor, comprising:

a first-level cache-memory unit that stores first data;

a second-level cache-memory unit that stores second data that includes the first data stored in the first-level cache-memory unit, and further stores validation information of the first data; and

a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on the validation information when a part of the second data is accessed.

2. The cache memory according to claim 1 , wherein the second-level cache-memory unit further stores a physical address of a tag relating to the second-level cache-memory unit, a status, and a virtual index, and

the physical address, the status, the virtual index, and the validation information are associated with each other.

3. The cache memory according to claim 1 , wherein the validation information includes a plurality of bits, and

the coherence maintaining unit acquires a registration status of the first-level cache-memory unit from the bits, and maintains the cache-coherence based on the registration status.

4. The cache memory according to claim 1 , wherein

the first-level cache-memory unit further stores a physical address of a tag relating to the first-level cache-memory unit, a status, and way information relating to a way that is registered in the second-level cache-memory unit; and

the physical address, the status, and the way information are associated with each other.

5. The cache memory according to claim 4 , further comprising a correcting unit that, when an error occurs in the first-level cache-memory unit, corrects the error based on the validation information and the way information.

6. The cache memory according to claim 5 , wherein,

the correcting unit determines whether there is error data that indicates occurrence of the error is updated, and

if the error data is updated, the correcting unit unloads the error data to the second-level cache-memory unit, and

if the error data is not updated, the correcting unit invalidates the error data.

7. A method for controlling a cache memory that passes data to a processor based on a request from the processor, wherein the cache memory includes a first cache-memory unit and a second cache memory unit, the first cache memory unit stores first data, and the second cache memory unit stores second data that include the first data the method comprising:

storing validation information of the first data to the second cache memory unit; and

maintaining cache-coherence between the first cache-memory unit and the second cache memory unit based on the validation information stored when a part of the second data is accessed.

8. The method according to claim 7 , wherein

the storing includes storing a physical address of a tag relating to the one of the cache-memory unit, a status, and a virtual index; and

the physical address, the status, the virtual index, and the validation information are associated with each other.

9. A method for controlling a cache memory that passes data to a processor based on a request from the processor, the cache memory includes a first cache-memory unit and a second cache memory unit, the first cache memory unit stores first data, and the second cache memory unit stores second data that includes the first data, the method comprising:

storing validation information of the first data to the second cache memory unit; and

correcting an error in the first cache-memory unit based on the validation information.

10. The method according to claim 9 , wherein,

the correcting includes determining whether there is error data that indicates occurrence of the error is updated, and

if the error data is updated, the correcting includes unloading the error data to other of the cache-memory unit, and

if the error data is not updated, the correcting includes invalidating the error data.

11. A cache memory comprising:

a first-level cache-memory unit that stores first data;

a second-level cache-memory unit that stores second data that includes the first data and validation information of the first data;

a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on the validation information;

a correcting unit correcting an error that occurs in the first-level cache-memory unit;

wherein the correcting unit determines whether there is error data that indicates occurrence of the error is updated, the correcting unit unloads the error data to the second-level cache-memory unit if the error data is updated, and the correcting unit invalidates the error data if the error data is not updated.