Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
View Patent ↗A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.
1. A method of forming a non-volatile memory cell having an access transistor and a capacitor structure, the method comprising:
forming a shallow trench isolation (STI) region in a first region of a semiconductor substrate;
forming a recessed region in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the first region;
forming a dielectric layer over the first region, including the sidewall region; and
forming a gate electrode over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region and forms a portion of the capacitor structure of the non-volatile memory cell.
2. A method of forming a non-volatile memory cell having an access transistor and a capacitor structure, the method comprising:
forming a shallow trench isolation (STI) region in a first region of a semiconductor substrate;
forming a recessed region in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the first region;
forming a capacitor region in the sidewall region;
forming a dielectric layer over the first region, including the sidewall region; and
forming a gate electrode over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region.
3. The method of claim 2 , wherein the steps of forming the recessed region and the capacitor region comprise:
forming a mask having an opening;
etching the STI region through the opening in the mask, thereby forming the recessed region; and
doping the capacitor region through the opening in the mask.
4. The method of claim 2 , further comprising forming the capacitor region as a p-type region.
5. The method of claim 2 , further comprising forming the capacitor region as an a-type region.
6. A method of forming a non-volatile memory cell having an access transistor and a capacitor structure, the method comprising:
forming a shallow trench isolation STI region in a first region of a semiconductor substrate;
forming a recessed region in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the first region;
forming a dielectric layer over the first region, including the sidewall region;
forming a gate electrode over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region; and
forming a dielectric spacer adjacent to the gate electrode, wherein the dielectric spacer extends over the sidewall region.
7. A method of forming a non-volatile memory cell having an access transistor and a capacitor structure, the method comprising:
forming a shallow trench isolation (STI) region in a first region of a semiconductor substrate;
forming a recessed region in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the first region;
forming a dielectric layer over the first region including the sidewall region, wherein the dielectric layer forms a gate
dielectric layer of the access transistor and a capacitor
dielectric layer of the capacitor structure; and forming a gate electrode over the dielectric layer, wherein a portion of the gate extends into the recessed region.