Patent Assignment
Reel/Frame 020741/0975
Change of Name
Recorded: 2008-04-03
Received: 2008-04-03
Pages: 8
Assignor
MONOLITHIC SYSTEM TECHNOLOGY, INC.
Executed: 2006-05-25
Assignee
MOSYS, INC.
755 NORTH MATHILDA AVENUE, SUNNYVALE, CA, 94085, UNITED STATES
Covered Properties
(54)
Scalable Embedded Dram Array
Application:
12/048,170 →
Scalable Embedded Dram Array
Application:
12/048,176 →
Non-Volatile Memory In CMOS Logic Process
Application:
12/045,557 →
Non-Volatile Memory In CMOS Logic Process
Application:
12/045,593 →
Error Detection/Correction Method
Application:
12/043,527 →
Method to Increase Charge Retention of Non-Volatile Memory Manufactured in a Single-Gate Logic Process
Application:
12/021,229 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,280 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,255 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,264 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
12/021,286 →
Fabrication Process For Increased Capacitance In An Embedded DRAM Memory
Application:
11/961,667 →
Embedded Memory And Multi-Media Accelerator And Method Of Operating Same
Application:
11/566,138 →
Word Line Driver for Dram Embedded in a Logic Process
Application:
11/559,870 →
Method for Enhanced Visualization of Medical Images
Application:
11/549,130 →
Scalable Embedded Dram Array
Application:
11/534,506 →
Dual-Port Sram Memory Using Single-Port Memory Cell
Application:
11/427,785 →
Non-Volatile Memory Embedded in a Conventional Logic Process and Methods for Operating Same
Application:
11/421,986 →
Non-Volatile Memory in Cmos Logic Process and Method of Operation Thereof
Application:
11/279,382 →
Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
Application:
11/341,881 →
Non-Volatile Memory in Cmos Logic Process
Application:
11/262,141 →
Transparent Error Correcting Memory That Supports Partial-Word Write
Application:
11/221,098 →
Word Line Driver for Dram Embedded in a Logic Process
Application:
11/166,856 →
Fabrication Process for Increased Capacitance in an Embedded Dram Memory
Application:
11/050,988 →
Non-Volatile Memory Cell Fabricated with Slight Modification to a Conventional Logic Process and Methods of Operating Same
Application:
10/999,259 →
Predictive Error Correction Code Generation Facilitating High-Speed Byte-Write in a Semiconductor Memory
Application:
10/997,604 →
High Speed Memory System
Application:
10/927,157 →
Error Detection/Correction Method
Application:
10/800,382 →
Method of Fabricating Vertical One-Transistor Floating-Body Dram Cell in Bulk Cmos Process with Electrically Isolated Charge Storage Region
Application:
10/705,112 →
Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
Application:
10/676,695 →
Transparent Error Correcting Memory
Application:
10/645,861 →
Method and Apparatus for Lengthening the Data-Retention Time of a Dram Device in Standby Mode
Application:
10/377,677 →
Dram Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
Application:
10/374,917 →
Dram Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
Application:
10/374,956 →
Non-Volatile Memory Cell Fabricated with Slight Modification to a Conventional Logic Process and Methods of Operating Same
Application:
10/355,477 →
Method and Apparatus for Temperature Adaptive Refresh in 1T-Sram Compatible Memory Using the Subthreshold Characteristics of Mosfet Transistors
Application:
10/300,427 →
Method and Apparatus for Completely Hiding Refresh Operations in a Dram Device Using Clock Division
Application:
10/279,363 →
Latched Sense Amplifiers as High Speed Memory in a Memory System
Application:
10/273,442 →
Method of Fabricating a Dram Cell Having a Thin Dielectric Access Transistor and a Thick Dielectric Storage Capacitor
Application:
10/231,800 →
Non-Volatile Memory Embedded in a Conventional Logic Process
Application:
10/165,589 →
Method and Apparatus for Completely Hiding Refresh Operations in a Dram Device Using Multiple Clock Division
Application:
10/114,282 →
One-Transistor Floating-Body Dram Cell in Bulk Cmos Process with Electrically Isolated Charge Storage Region
Application:
10/095,901 →
Vertical One-Transistor Floating-Body Dram Cell in Bulk Cmos Process with Electrically Isolated Charge Storage Region
Application:
10/095,984 →
Reduced Topography Dram Cell Fabricated Using a Modified Logic Process and Method for Operating Same
Application:
10/043,386 →
Error Correcting Memory and Method of Operating Same
Application:
10/003,602 →
Dram Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
Application:
10/033,690 →
Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same
Application:
10/007,334 →
High-Speed Read-Write Circuitry for Semi-Conductor Memory Devices
Application:
09/963,984 →
Non-Volatile Memory System
Application:
09/948,163 →
Memory Modules with High Speed Latched Sense Amplifiers
Application:
09/903,094 →
Apparatus for Controlling Data Transfer Between a Bus and Memory Array and Method for Operating Same
Application:
09/851,713 →
Method and Apparatus for Completely Hiding Refresh Operations in a Dram Device Using Clock Division
Application:
09/846,093 →
Method and Apparatus for Forcing Idle Cycles to Enable Refresh Operations in a Semiconductor Memory
Application:
09/795,750 →
Reduced Topography Dram Cell Fabricated Using a Modified Logic Process and Method for Operating Same
Application:
09/772,434 →
Single-Port multi-bank memory system having read and write buffers and method of operating same
Application:
09/768,908 →