In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
1. A MOS transistor, comprising:
a semiconductor substrate region having N-type conductivity type;
a first diffusion layer having P-type conductivity type, being provided in said semiconductor substrate region;
a second diffusion layer having P-type conductivity type, being provided in said semiconductor substrate region;
a channel region, being provided between said first diffusion layer and said second diffusion layer in an interior of said semiconductor substrate region;
a gate insulating film, comprising a high dielectric constant film having higher dielectric constant than silicon oxide and being provided on said channel region; and
a gate electrode, comprising polycrystalline silicon containing N-type impurity and being provided on said gate insulating film, the gate electrode sufficiently doped with the N-type impurity to inhibit gate depletion in the presence of Fermi level pinning occurring by diffusion within the high dielectric constant film.
2. The MOS transistor according to claim 1 , wherein said high dielectric constant film contains one or more element (s) selected from a group consisting of Hf, Zr, Al, La and Y.
3. The MOS transistor according to claim 1 , wherein P-type impurity is introduced into said channel region.
4. The MOS transistor according to claim 1 , further comprising a N-type impurity region under said channel region, said N-type impurity region containing N-type impurity introduced therein.
5. The MOS transistor according to claim 1 , wherein said gate insulating film comprises a silicon oxide film and said high dielectric constant film provided thereon, and wherein said high dielectric constant film is in contact with said gate electrode.
6. The MOS transistor according to claim 1 , wherein said high dielectric constant film contains one or more element(s) selected from a group consisting of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, and yttrium oxide.
7. The MOS transistor according to claim 6 , wherein the high dielectric constant film contains nitrogen from annealing within an atmosphere of a nitrogen-containing compound.
8. The MOS transistor according to claim 1 , wherein said high dielectric constant film has a specific dielectric constant of equal to or higher than 10.
9. The MOS transistor according to claim 8 , wherein the high dielectric constant film is hafnium silicate.
10. The MOS transistor according to claim 8 , wherein the high dielectric constant film is non-crystallized hafnium silicate containing nitrogen.
11. The MOS transistor according to claim 10 , wherein,
the gate electrode is sufficiently doped with the N-type impurity so that even if Fermi level pinning occurs by diffusion of hafnium, gate depletion is inhibited.
12. The MOS transistor according to claim 8 , wherein the high dielectric constant film is an oxynitride of one of the group consisting of Hf, Zr, Al, La, and Y.
13. The MOS transistor according to claim 8 , wherein the high dielectric constant film is an oxynitride of one of the group consisting of Hf, Zr, Al, La, and Y.
14. The MOS transistor according to claim 1 , wherein the high dielectric constant film is hafnium silicate.
15. The MOS transistor according to claim 1 , wherein the high dielectric constant film is non-crystallized hafnium silicate containing nitrogen.
16. The MOS transistor according to claim 15 , Wherein,
the channel region comprised buried In, the MOS transistor functions as a buried channel transistor,
the gate electrode is sufficiently doped with the N-type impurity so that even if Fermi level pinning occurs by diffusion of hafnium, gate depletion is inhibited.
17. The MOS transistor according to claim 16 , further comprising:
a punchthrough stopper region provided adjacently below the channel region.
18. A MOS transistor, comprising:
a semiconductor substrate region having N-type conductivity type;
a first diffusion layer having P-type conductivity type, being provided in said semiconductor substrate region;
a second diffusion layer having P-type conductivity type, being provided in said semiconductor substrate region;
a channel region, being provided between said first diffusion layer and said second diffusion layer in an interior of said semiconductor substrate region;
a gate insulating film, provided on said channel region, comprising a silicon oxide gate insulating film adjacent a high dielectric constant film of hafnium having a higher dielectric constant than the silicon oxide; and
a gate electrode, comprising polycrystalline silicon containing N-type impurity and being provided adjacent the high dielectric film, the gate electrode sufficiently doped with the N-type impurity to inhibit gate depletion in the presence of Fermi level pinning occurring by diffusion of the hafnium within the high dielectric constant film.
19. The MOS transistor of claim 18 , wherein, the high dielectric constant film comprises one of an oxide, a silicate, and an oxynitride of hafnium, and the silicon oxide film is approximately 1.2nm to 1.5 nm thick.
20. The MOS transistor of claim 18 , wherein, the silicon oxide film is approximately 1.2nm to 1.5 nm thick.