Semiconductor storage device
A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix form, a plurality of word lines connected to the memory cells, a row decoder including a plurality of decode sections and configured to receive first and second address signals for selecting the word lines, each of the decode sections which is provided for a respective one of the word lines, and includes first and second MOS transistors connected in series, the first MOS transistor having its gate electrode connected to receive the first address signal, the second MOS transistor having its gate electrode connected to receive the second address signal, the row decoder outputting a first signal for controlling the word lines, and a control circuit which delays the second address signal in time with respect to the first address signal.
1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix form;
a plurality of word lines connected to the memory cells;
a row decoder including a plurality of decode sections and configured to receive first and second address signals for selecting the word lines, each of the decode sections which is provided for a respective one of the word lines, and includes first and second MOS transistors connected in series, the first MOS transistor having its gate electrode connected to receive the first address signal, the second MOS transistor having its gate electrode connected to receive the second address signal, the row decoder outputting a first signal for controlling the word lines; and
a control circuit which delays the second address signal in time with respect to the first address signal.
2. The semiconductor memory device according to claim 1 , wherein each of the decode sections includes a first power supply which supplies a first voltage for driving the word lines, a third MOS transistor connected between the first power supply and the first MOS transistor and having its gate electrode connected to receive a second signal for placing the memory cell array in an active state or a precharged state, a second power supply which supplies ground potential and is connected to the second MOS transistor, and a connection node which connects the first MOS transistor and the third MOS transistor and outputs decoded data corresponding to the first signal, and wherein the third MOS transistor supplies the connection node with the first voltage when its gate electrode receives the second signal indicating the precharged state, and does not supply the connection node with the first voltage when its gate electrode receives the second signal indicating the active state.
3. The semiconductor memory device according to claim 2 , wherein the first and second signals have the first voltage, and the first and second address signals have a second voltage lower than the first voltage.
4. The semiconductor memory device according to claim 3 , wherein the first and second MOS transistors have a threshold voltage corresponding to the second voltage and the third MOS transistor has a threshold voltage corresponding to the first voltage.
5. The semiconductor memory device according to claim 2 , wherein the row decoder includes a latch circuit which latches the decoded data at the connection node.
6. The semiconductor memory device according to claim 1 , further comprising a drive circuit which drives the word lines on the basis of the first signal.