Semiconductor device and manufacturing process therefore
View Patent ↗A semiconductor device which can prevent a leak current between a silicide layer on a polysilicon and another part, as well as a manufacturing process therefor. The semiconductor device includes neighboring n- and p-type polysilicons; and a silicide layer thereon extending from the n-type polysilicon to the p-type polysilicon. The silicide layer is formed over the upper surfaces of the n- and p-type polysilicons except the periphery thereof.
1. A semiconductor device comprising:
neighboring n- and p-type polysilicons; and
a silicide layer thereon extending from said n-type polysilicon to said p-type polysilicon,
wherein said silicide layer is formed over upper surfaces of said n- and p-type polysilicons except a periphery thereof.
2. A semiconductor device comprising:
neighboring n- and p-type polysilicons; and
a silicide layer thereon extending from said n-type polysilicon to said p-type polysilicon,
wherein said silicide layer is formed on a border region of said n- and p- type polysilicons without contacting any edges of said n- and p-type polysilicons.
3. The semiconductor device according to claim 1 , wherein said silicide layer is formed only in a border and its neighboring area between said n- and said p-type polysilicons.
4. The semiconductor device according to claim 2 , wherein said silicide layer is formed only in a border and its neighboring area between said n- and p-type polysilicons.
5. The semiconductor device according to claim 3 , wherein in said n- and p-type polysilicons, a region on which said silicide layer is to be formed and its neighboring area are broader than a surrounding area.
6. The semiconductor device according to claim 4 , wherein in said n- and p-type polysilicons, a region on which said silicide layer is to be formed and its neighboring area are broader than a surrounding area.
7. The semiconductor device according to claim 1 , further comprising an interlayer insulating film over said silicide layer and said n- and said p-type polysilicons,
wherein said interlayer insulating film have a first and a second contacts in areas corresponding to said n- and said p-type polysilicons, respectively, each of which is connected to said silicide layer.
8. The semiconductor device according to claim 2 , further comprising an interlayer insulating film over said silicide layer and said n- and said p-type polysilicons,
wherein said interlayer insulating film have a first and a second contacts in areas corresponding to said n- and said p-type polysilicons, respectively, each of which is connected to said silicide layer.
9. The semiconductor device according to claim 1 , wherein said n-type polysilicon acts as an n-gate while said p-type polysilicon acts as a p-gate.
10. The semiconductor device according to claim 2 , wherein said n-type polysilicon acts as an n-gate while said p-type polysilicon acts as a p-gate.
11. The semiconductor device according to claim 9 , wherein said semiconductor device comprises at least a DRAM, whose cell comprises said n- and said p-gates and said silicide layer.
12. The semiconductor device according to claim 10 , wherein said semiconductor device comprises at least a DRAM, whose cell comprises said n- and said p-gates and said silicide layer.
13. The semiconductor device according to claim 9 , wherein said semiconductor device comprises at least a nonvolatile memory, whose cell comprises said n- and said p-gates and said silicide layer.
14. The semiconductor device according to claim 10 , wherein said semiconductor device comprises at least a nonvolatile memory, whose cell comprises said n- and said p-gates and said silicide layer.
15. A process for manufacturing a semiconductor device comprising:
forming neighboring n- and p-type polysilicons; and
forming a silicide layer extending from said n-type polysilicon to said p-type polysilicon, said silicide layer being formed on a border region of said n- and p-type polysilicons without contacting any edges of said n- and p-type polysilicons.
16. The process for manufacturing a semiconductor device according to claim 15 , wherein said forming a silicide layer comprises
forming a mask over said upper surface of said polysilicons which covers said periphery of said upper surface and has an opening around a border between said n- and said p-type polysilicons;
then forming a metal layer over a whole upper surfaces of said n- and said p-type polysilicons; and
siliciding at least part of said metal layer.
17. The process for manufacturing a semiconductor device according to claim 15 , wherein in said forming a silicide layer, said silicide layer is formed only in said border and its neighboring area between said n- and said p-type polysilicons.
18. The process for manufacturing a semiconductor device according to claim 17 , wherein in said forming polysilicons, said n- and p-type polysilicons are formed such that a region on which said silicide layer is to be formed and its neighboring area is broader than a surrounding area.
19. The process for manufacturing a semiconductor device according to claim 15 , further comprising:
forming an interlayer insulating film over said silicide layer and said n- and said p-type polysilicons; and
forming in said interlayer insulating film a first and a second contacts corresponding to said n- and said p-type polysilicons, respectively, each of which is connected to said silicide layer.
20. The semiconductor device according to claim 1 , wherein said silicide layer electrically connects said n- and p-type polysilicons.