Semiconductor integrated circuit device

1. A semiconductor IC device in which an electrostatic protective circuit is connected to an internal circuit connected between two pads including a power-supply pad and a signal input/output pad, the internal circuit comprising a matching circuit for adjusting the impedance between the two pads,

said matching circuit comprising:

n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads, the resistance of each of the resistance elements being set to a larger value than a required impedance between the two pads;

n×m (m is a positive number of 2 or more) transistors, wherein the m transistors in each set of m transistors are connected in parallel to each other, and wherein each said set of m transistors is connected in series to a respective one of the n resistance elements; and

an adjustor for selectively allowing the transistors to perform an ON-operation,

wherein the transistors comprise MOS transistors and the sources and drains thereof are connected in series to the resistance elements, respectively,

wherein the n×m MOS transistors are laid out in the same diffusion-layer region, and

wherein each of the m MOS transistors has a same gate width and the gate width satisfies the equations:

Wx×Idg×Rt+Vsp>Vesd; and

Wx=W 1 ×N,

where Wx is a total gate width of the MOS transistors performing a bipolar operation together when a surge current is applied,

W 1 is a gate width of each MOS transistor,

N is the number of MOS transistors performing a bipolar operation (1≦N≦m),

Idg is a value of breakdown current for the gate width of each MOS transistor,

Rt is an electrical resistance of MOS transistor (total resistance in a path from a source pad to a drain pad of the MOS transistor),

Vsp is a snapback voltage in the MOS transistor performing a bipolar operation, and

Vesd is a maximum voltage required by an electrostatic protective circuit for dissipating a surge current.

2. A semiconductor IC device according to claim 1 , wherein a protective transistor of the electrostatic protective circuit comprises a MOS transistor and the following equation is satisfied:

Wx×Rt>Wesd×Resd

where Wesd is a gate width of a MOS transistor in the electrostatic protective circuit (total gate width of a plurality of MOS transistors connected in parallel that are connected in parallel to a ballast resistor), and Resd is a resistance of the ballast resistor.

3. A semiconductor IC device according to claim 2 , where N=1, so that Wx=W 1 .

4. A semiconductor IC device in which an electrostatic protective circuit is connected to an internal circuit connected between two pads including a power-supply pad and a signal input/output pad, the internal circuit comprising a matching circuit for adjusting the impedance between the two pads,

said matching circuit comprising:

n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads, the resistance of each of the resistance elements being set to a larger value than a required impedance between the two pads;

n×m (m is a positive number of 2 or more) transistors, wherein the m transistors in each set of m transistors are connected in parallel to each other, and wherein each said set of m transistors is connected in series to a respective one of the n resistance elements; and

an adjustor for selectively allowing the transistors to perform an ON-operation,

wherein the transistors comp rise MOS transistors and the sources and drains thereof are connected in series to the resistance elements, respectively,

wherein the n×m MOS transistors are laid out in the same diffusion-layer region, and

wherein each of the m MOS transistors has a same gate width and the gate width satisfies the equation:

m×W 1× Idg×Rt+Vsp>Vesd

where W 1 is a gate width of each MOS transistor,

Idg is a value of breakdown current for the gate width of each MOS transistor,

Rt is an electrical resistance of the MOS transistor (total resistance in a path from a source pad to a drain pad of the MOS transistor),

Vsp is a snapback voltage in the MOS transistor performing a bipolar operation, and

Vesd is a maximum voltage required by an electrostatic protective circuit for dissipating a surge current.

5. A semiconductor IC device in which an electrostatic protective circuit is connected to an internal circuit connected between two pads including a power-supply pad and a signal input/output pad, the internal circuit comprising a matching circuit for adjusting the impedance between the two pads,

said matching circuit comprising:

n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads, the resistance of each of the resistance elements being set to a larger value than a required impedance between the two pads;

n×m (m is a positive number of 2 or more) transistors, wherein the m transistors in each set of m transistors are connected in parallel to each other, and wherein each said set of m transistors is connected in series to a respective one of the n resistance elements; and

an adjustor for selectively allowing the transistors to perform an ON-operation,

wherein the transistors comprise MOS transistors and the sources and drains thereof are connected in series to the resistance elements, respectively,

wherein the n×m MOS transistors are laid out in the same diffusion-layer region, and

wherein a ballast resistor and a protective transistor are connected in series in the electrostatic protective device.