Thin film diode integrated with chalcogenide memory cell
View Patent ↗An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge 2 Se 8 or Ge 25 Se 75 ). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element. Methods of fabricating integrated programmable conductor memory cell and diode devices are also disclosed.
1. A method for making a variable resistance memory cell with an integrated thin film diode in a via, comprising:
providing a diffusion barrier material at a bottom of the via;
depositing a first chalcogenide glass to fill the via;
etching the first chalcogenide glass back to form a recess in the via;
doping the first chalcogenide glass to a depth after etching;
forming a mixture of a second chalcogenide glass and a first conductive material to fill the via after doping; and
depositing a second conductive material over the mixture.
2. The method of claim 1 , wherein the first chalcogenide glass and the second chalcogenide glass each comprise germanium (Ge) and selenium (Se).
3. The method of claim 2 , wherein the first chalcogenide glass and the second chalcogenide glass comprise Ge 2 Se 8 or Ge 25 Se 75 .
4. The method of claim 1 , wherein the first chalcogenide glass is deposited by sputtering.
5. The method of claim 1 , wherein the first chalcogenide glass is deposited by evaporating.
6. The method of claim 1 , wherein etching the first chalcogenide glass back comprises an isotropic etch.
7. The method of claim 6 , wherein the isotropic etch comprises a CF 4 dry etch.
8. The method of claim 6 , wherein the isotropic etch is an aqueous base.
9. The method of claim 6 , wherein the isotropic etch comprises tetramethyl ammonium hydroxide (TMAH).
10. The method of claim 6 , wherein the isotropic etch comprises ammonium hydroxide.
11. The method of claim 1 , wherein doping the first chalcogenide glass comprises processing at a temperature less than about 340° C.
12. The method of claim 11 , wherein doping the first chalcogenide glass comprises ion implantation.
13. The method of claim 12 , wherein ion implantation comprises a species selected from the group consisting of bismuth and lead.
14. The method of claim 13 , wherein the ion implantation is performed at an energy between about 20 keV and 30 keV at a dose between about 1×10 13 atoms/CM 2 and 1×10 14 atoms/CM 2 .
15. The method of claim 11 , wherein doping the first chalcogenide glass to a depth comprises doping to a depth of between about 10 nm and 20 nm, thereby forming a p-n junction with the underlying chalcogenide glass.
16. The method of claim 11 , wherein doping the first chalcogenide glass to a depth comprises doping through an entire depth of the chalcogenide glass, thereby forming a p-n junction at a boundary of the first, doped chalcogenide glass and the mixture of the second chalcogenide glass and the first conductive material.
17. The method of claim 1 , wherein forming the mixture of the second chalcogenide glass and the first conductive material comprises co-sputtering germanium selenide from a pressed powder target and silver from a silver target.
18. The method of claim 1 , wherein depositing the second conductive material over the mixture of the second chalcogenide glass and the first conductive material comprises depositing a layer of second conductive material selected from the group consisting of Group IB or Group IIB metals to a thickness of about 50 nm to about 100 nm.
19. The method of claim 18 , wherein both the first conductive material and the second conductive material comprise silver.
20. The method of claim 19 , further comprising patterning the second conductive material to form a top electrode for the variable resistance memory cell.
21. The method of claim 20 , further comprising providing conducting lines, in contact with the top electrode for the variable resistance memory cell and providing connections to other variable resistance memory cells.
22. The method of claim 21 , wherein the conducting lines comprise tungsten.
23. A method of fabricating a programmable memory device wherein each memory cell has an ancillary diode, comprising:
etching a via in a silicon nitride layer over a tungsten region;
filling the via with germanium selenide (Ge—Se);
etching back the Ge—Se to form a recess in the via;
ion implanting the Ge—Se with bismuth;
co-sputtering a mixture of Ge—Se and silver (Ag)
depositing and patterning a silver layer onto the mixture of Ge—Se and Ag to form a top electrode; and
depositing a top conducting layer of tungsten.
24. A method of forming a memory cell, comprising:
providing a polysilicon diode;
forming a diffusion barrier layer over the polysilicon diode;
depositing germanium selenide glass over the diffusion barrier layer; and
infusing the germanium selenide glass with metal ions.