Semiconductor integrated circuit device
View Patent ↗In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.
1. A semiconductor integrated circuit device receiving a command and an aDDRess, comprising:
a command decoder for decoding the command and outputting decode pulses;
a command counter circuit for counting the decode pulses as the number of commands;
a latch circuit for latching the aDDRess in response to a count output from the command counter circuit;
a latency counter circuit for counting a latency in response to the decode pulses;
a first output circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value; and
a second output circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on.
2. The semiconductor integrated circuit device according to claim 1 , wherein the command is one of a write command and a read command.
3. The semiconductor integrated circuit device according to claim 1 , wherein the semiconductor integrated circuit device is a DDR-II SDRAM.
4. A semiconductor integrated circuit device receiving a write command and a write aDDRess, comprising:
a write command decoder for decoding the write command and outputting decode pulses;
a command counter circuit for counting the decode pulses as the number of commands;
a latch circuit for latching the write aDDRess in response to a count output from the command counter circuit;
a latency counter circuit for counting a latency in response to the decode pulses;
a first output circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value; and
a second output circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on;
wherein a write operation to the column aDDRess is carried out in response to the column selection control signal being turned on.
5. The semiconductor integrated circuit device according to claim 4 , wherein the semiconductor integrated circuit device is a DDR-II SDRAM.
6. A semiconductor integrated circuit device receiving a read command and a read aDDRess, comprising:
a read command decoder for decoding the read command and outputting decode pulses;
a command counter circuit for counting the decode pulses as the number of commands;
a latch circuit for latching the read aDDRess in response to a count output from the command counter circuit;
a latency counter circuit for counting a latency in response to the decode pulses;
a first output circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value; and
a second output circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on;
wherein a read operation to the column aDDRess is carried out in response to the column selection control signal being turned on.
7. The semiconductor integrated circuit device according to claim 6 , wherein the semiconductor integrated circuit device is a DDR-II SDRAM.