Semiconductor integrated circuits with power reduction mechanism
View Patent ↗Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
1. A semiconductor integrated circuit comprising:
a plurality of word lines including a first group of word lines and a second group of word lines;
a plurality of data lines crossing said plurality of word lines;
a plurality of memory cells disposed at points of intersection of said plurality of word lines and said plurality of data lines;
a first block including a first group of word drivers disposed at a first region in a direction extended from said data lines; and
a second block including a second group of word drivers disposed at a second region in a direction extended from said data lines,
wherein each of said first group of word lines connected with said first group of word drivers is disposed adjacently to each of said second group of word lines connected with said second group of word drivers;
wherein said first region and said second region are disposed in a direction extended from said word lines and in a shifted position relative to each other,
wherein said first block includes a first power supply line to supply an operating voltage to said first group of word drivers, said first power supply line being controlled by a first current limiting circuit,
wherein said second block includes a second power supply line to supply an operating voltage to said second group of word drivers, said second power supply line being controlled by a second current limiting circuit,
wherein a subthreshold current of an MOS transistor included in said first group of word drivers is limited by said first current limiting means as to said first block, and an operating voltage is supplied to said second power supply line included in said second block through said second current limiting circuit to place said second group of word drivers in an operable state.
2. A semiconductor integrated circuit according to claim 1 , wherein an subthreshold current of an MOS transistor included in said second group of word drivers is limited by said second current limiting circuit as to said second block, and an operating voltage is supplied to said first power supply line included in said first block through said first current limiting circuit to place said first group of word drivers in an operable state.
3. A semiconductor integrated circuit according to claim 1 , wherein said first region and said second region are disposed adjacently each other.
4. A semiconductor integrated circuit according to claim 2 , wherein said first region and said second region are disposed adjacently each other.