IP Library Granted Patent US 7,339,938
Granted Patent B2
US 7,339,938 · App. 11/006,563 · Granted Mar 4, 2008

Linked network switch configuration

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Quick Facts
Patent No.
US 7,339,938
App. No.
11/006,563
Granted
Mar 4, 2008
Kind
B2
Abstract

System and method for integrating communications between two switches. The system includes a first switch, a second switch and a CPU. The first switch has a first plurality of ports, and the second switch has a second plurality of ports. The CPU is coupled to the first switch and the second switch, and is configured to control and program the first and second switch. A port of the first plurality of ports, as a first link port, is coupled to a port of the second plurality of ports, as a second link port. The first plurality of ports are designated by a first numbering scheme, the second plurality of ports are designated by a second numbering scheme, and the first and second link ports each have a tag insertion unit, a processing unit and a removing unit, for inserting an inter-stack tag, processing the packet, and removing the inter-stack tag.

Claims (22)

1. A method for integrating a plurality of switches into a network device, comprising the steps of:

designating a first plurality of ports of a first switch by a first numbering scheme;

designating a second plurality of ports of a second switch by a second numbering scheme different than said first numbering scheme;

coupling a first link port of said first plurality of ports to a second link port of said second plurality of ports;

configuring said first and second switches to insert an inter-stack tag into a packet received at a first network port of said first plurality of ports, said inter-stack tag having a source address related to said first network port according to said first numbering scheme and to relay said packet to said second switch via said first and second link ports; and

configuring said first and second switches to learn said source address, to remove said inter-stack tag from said packet, and to relay said packet to a destination port of said second plurality of second based on said inter-stack tag.

2. The method of claim 1 , wherein said configuring said first and second switches to insert step includes configuring said first switch to insert an inter-stack tag which includes data relating to said first numbering when said data packet is received at said first switch, and said second switch to insert an inter-stack tag which includes data relating to said second numbering scheme when said data packet is received at said second switch.

3. The method of claim 1 further comprising the steps of:

configuring said first and second switches to perform address resolution based on said first numbering scheme and said second numbering scheme and said inter-stack tag.

4. The method of claim 1 , wherein said designating step includes designating said first switch based on a first pin designating said first plurality of ports by said first numbering scheme and designating said second switch based on a second pin designating said second plurality of ports by said second numbering scheme.

5. A method of switching data packets within a plurality of switches, comprising the steps of:

providing a first switch having a first plurality of ports designated by a first numbering scheme coupled to a second switch having a second plurality of ports designated by a second numbering scheme different than said first numbering scheme, said first and second switch being coupled by a first link port of said first plurality of ports coupled to a second link port of said second plurality of ports;

receiving a packet at a first network port of said first plurality of ports;

inserting a inter-stack tag into said packet, said inter-stack tag having a source address related to said first network port according to said first numbering scheme;

relaying said packet to said second switch via said first and second link ports;

learning said source address at said second switch;

removing said inter-stack tag from said packet; and

relaying said packet to a destination port of said second plurality of second based on said inter-stack tag.

6. The method of claim 5 , wherein said inserting step includes inserting the inter-stack tag which includes data relating to said first numbering when said data packet is received at said first switch, and inserting an inter-stack tag which includes data relating to said second numbering scheme when said data packet is received at said second switch.

7. The method of claim 5 , further comprising the steps of:

performing address resolution based on said first numbering scheme and said second numbering scheme and said inter-stack tag.

8. The method of claim 5 , wherein said providing step includes designating said first plurality of ports by said first numbering scheme based on a first pin of said first switch and designating said second plurality of ports by said second numbering scheme based on a second pin of said second switch.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →