IP Library Granted Patent US 7,148,137
Granted Patent B2
US 7,148,137 · App. 11/008,152 · Granted Dec 12, 2006

Method of forming metal line in semiconductor device

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Quick Facts
Patent No.
US 7,148,137
App. No.
11/008,152
Granted
Dec 12, 2006
Kind
B2
Abstract

A method of forming a metal line in a semiconductor device. The method includes forming an insulating interlayer over a substrate provided with a lower metal line, and forming a hole exposing the lower metal line. The method also includes forming a first metal layer on the insulating interlayer including an inside of the hole and the lower metal line, forming a conductor layer on the first metal layer to fill the hole, and etching back the conductor layer to form a plug until the first metal layer is exposed. The method further includes stacking a second metal layer and a third metal layer on the first metal layer, and patterning the second metal layer, the third metal layer, and the first metal layer to form an upper metal line overlapped with the plug using an etch mask defining the upper metal line.

Claims (13)

1. A method of forming a metal line in a semiconductor device, comprising the steps of:

forming an insulating interlayer over a substrate provided with a lower metal line;

forming a hole exposing the lower metal line;

forming a first metal layer on the insulating interlayer including an inside of the hole and the lower metal line;

forming a conductor layer on the first metal layer to fill the hole;

etching back the conductor layer to form a plug and stopping the etching back when the first surface of metal layer is exposed;

sequentially stacking a second metal layer and a third metal layer on the first metal layer and the plug; and

patterning the second metal layer, the third metal layer, and the first metal layer to form an upper metal line overlapped with the plug using an etch mask defining the upper metal line.

2. The method of claim 1 , further comprising the step of removing the etch mask.

3. The method of claim 1 , wherein the first and third metal layers are formed of Ti or TiN.

4. The method of claim 1 , wherein the second metal layer is formed of aluminum.

5. The method of claim 1 , wherein the conductor layer is formed of tungsten.

6. The method of claim 1 , wherein the etching back step includes chemical mechanical polishing.

Assignments (2)
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2004
From: KIM, JUNG HO
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 016081/0383 →