VLIW digital signal processor for achieving improved binary translation
View Patent ↗A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th banks store therein first to n-th programs, respectively. The first to n-th address counters respectively indicates addresses at which next instructions to be executed next, selected out of VLIW instructions within said first to n-th programs, are stored in said first to n-th banks. The fetch block is configured to fetch said next instructions from said addresses, respectively, and to generate a resultant VLIW instruction from said next instructions. The instruction executing section is configured to receive said resultant VLIW instruction, and to execute said resultant VLIW instruction in a single instruction executing cycle.
1. A digital signal processor comprising:
a program memory including a plurality of banks storing a plurality of programs, each of the programs including a plurality of instructions;
a plurality of address counters storing addresses at which ones of the instructions are stored, said ones of the instructions to be executed in a next instruction execution cycle, and said addresses being correlated with said plurality of banks;
a fetch block configured to fetch the instructions stored at the addresses stored by at least two of the address counters, from the banks corresponding to the addresses stored by said at least two of the address counters, a first one of the fetched instructions corresponding to a first program of the programs and a second one of the fetched instructions corresponding to a second program of the programs, and to combine said fetched instructions to generate a reallocated instruction;
a plurality of register files; and
an instruction executing section configured to receive said reallocated instruction and to execute said reallocated instruction in said next instruction executing cycle,
wherein said fetch block is configured to, when one of said plurality of register files includes both a first register described in said instructions of said first program and a second register described in said instructions of said second program, rewrite said fetched instructions so as to replace said first register with a third register which is not incorporated within said one of said plurality of register files, and to generate said reallocated instruction by combining said rewritten instructions.
2. The digital signal processor according to claim 1 , further comprising a plurality of program counter registers storing respective start addresses of said plurality of programs;
wherein said start addresses stored in said plurality of program counter registers are transferred to one of said plurality of address counters associated with said plurality of program counter registers, respectively.
3. The digital signal processor according to claim 1 ,
wherein said instruction executing section comprises:
a decode block configured to receive said reallocated instruction and generate subinstructions from said reallocated instruction;
a dispatch block; and
a plurality of execution units,
wherein said dispatch block supplies execution control signals to said plurality of execution units in response to said subinstructions, and
wherein each of said execution units performs an associated one of operations specified by said subinstructions in response to said execution control signals.
4. The digital signal processor according to claim 3 ,
wherein said execution units comprise:
a plurality of multiplier-accumulator units; and
a plurality of arithmetic-logic units.
5. A method of operating a digital signal processor, the method comprising;
i. storing, at a plurality of banks, a plurality of programs, each of the programs including a plurality of instructions;
ii. storing, at a plurality of address counters, addresses at which ones of the instructions are stored, said ones of the instructions to be executed in a next instruction execution cycle, and said addresses being correlated with said plurality of banks;
iii. receiving the instructions stored at the addresses stored by at least two of the address counters, from the banks corresponding to the addresses stored by said at least two of the address counters, a first one of the received instructions corresponding to a first program of the programs, and a second one of the received instructions corresponding to a second program of the programs;
iv. generating a reallocated instruction by combining said received instructions; and
v. executing said reallocated instruction in said next instruction executing cycle,
vi. wherein generating the reallocated instruction comprises, when one of a plurality of register files includes both a first register described in said instructions of said first program and a second register described in said instructions of said second program, rewriting said received instructions so as to replace said first register with a third register which is not incorporated within said one of said plurality of register files, and combining said rewritten instructions.