Metal interconnection lines of semiconductor devices and methods of forming the same

1. A method of forming a metal interconnection line of a semiconductor device, comprising:

forming a glue layer on a semiconductor substrate;

forming dummy patterns on the glue layer;

forming a metal pattern to fill a gap between the dummy patterns;

forming an anti-reflection layer;

forming a photoresist layer pattern on the anti-reflection layer to mask the metal pattern and portions of the dummy patterns adjacent the metal pattern;

forming a metal interconnection line by etching the anti-reflection layer, the dummy patterns, and the glue layer using the photoresist layer pattern as a mask; and

removing the photoresist layer pattern.

2. A method as defined in claim 1 , wherein forming the dummy patterns comprises:

forming a dummy layer on the glue layer; and

patterning the glue layer to expose the glue layer.

3. A method as defined in claim 2 , wherein the dummy patterns comprise titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

4. A method as defined in claim 2 , wherein a thickness of the metal pattern and a thickness of the dummy patterns are substantially identical.

5. A method as defined in claim 1 , wherein forming the metal pattern comprises:

forming a metal layer on an entire surface of the substrate and dummy patterns to fill gaps between the dummy patterns; and

performing a planarization process to expose surfaces of the dummy patterns.

6. A method as defined in claim 5 , wherein the metal pattern comprises Al, Cu, Al—Cu, or Al—Cu—Si.

7. A method as defined in claim 1 , wherein in the etching performed in forming the metal interconnection line is dry etching.

8. A method as defined in claim 1 , wherein the glue pattern is a Ti layer, TiN layer, or Ti/TiN layer.

9. A method as defined in claim 1 , wherein the anti-reflection pattern is a Ti/TiN layer.