Methods of fabricating semiconductor devices having salicide

1. A method for fabricating a semiconductor device with salicide, comprising:

forming a gate electrode structure having a gate oxide film, a gate electrode, and a protection film stacked on a substrate in succession, and gate spacers on sidewalls of the stack of the gate oxide film, the gate electrode, and the protection film;

forming an insulating film on an entire surface of the substrate, the insulating film exposing upper portions of the gate electrode and the gate spacers;

removing portions of the protection film and the gate spacers, to expose an upper portion of the gate electrode;

applying a salicide forming metal on an entire surface of the substrate; and

performing a heat treatment process to form salicide on the gate electrode and the gate spacers, selectively.

2. A method as defined in claim 1 , wherein forming the gate electrode structure includes;

stacking gate oxide, gate polysilicon, buffer oxide, and nitride on the substrate in succession,

performing selective etching with an etch mask, to remove portions of the nitride, the buffer oxide, and the gate polysilicon in succession, to expose a portion of an upper portion of the gate oxide selectively, and

forming the gate spacers on the sidewalls of the stack of the gate oxide film, the gate electrode, and the protection film, to form the gate electrode structure having the stack of the gate oxide, the gate electrode, and the protection film with the buffer oxide, and the nitride.

3. A method as defined by claim 2 , wherein the buffer oxide has a thickness ranging from about 150 Å to 300 Å.

4. A method as defined by claim 3 , wherein the buffer oxide is deposited by CVD, or PE-CVD.

5. A method as defined by claim 1 , wherein forming the insulating film includes;

applying insulating material on an entire surface of the substrate in a form the insulating material buries the gate electrode structure,

planarizing an upper portion of the insulating material,

removing a portion of an upper portion of the insulating material, to expose an upper portion of the protection film, and

removing upper portions of the protection film and the gate spacers, for forming the insulating film which exposes upper portions of the gate electrode and the gate spacers.

6. A method as defined by claim 5 , wherein the planarizing is made by CMP.

7. A method as defined by claim 5 , wherein the portion of the upper portion of the insulating material is planarized by wet, or dry etching.

8. A method as defined by claim 5 , wherein the protection film includes a stack of a buffer oxide film and a nitride film.

9. A method as defined by claim 8 , wherein the portions of upper portions of the nitride film and the gate spacers are etched by wet etching with a chemical, or dry etching.

10. A method as defined by claim 9 , wherein the chemical includes hot phosphoric acid.

11. A method as defined by claim 9 , wherein the dry etching is performed by using a combination of an F-group gas, such as CF 4 , SF 6 , or NF 3 , and an additive gas of O 2 , N 2 , Ar, or He.

12. A method as defined by claim 8 , wherein the buffer oxide film is removed by wet etching with a chemical containing HF, or dry etching.

13. A method as defined by claim 1 , wherein forming the insulating film includes;

applying insulating material on an entire surface of the substrate in a form the insulating material buries the gate electrode structure,

performing full surface etching taking the protection film as an etch stop point, to expose upper portions of the protection film and the gate spacers, and

removing a portion of each of upper portions of the protection film and the gate spacers, for forming the insulating film which exposes upper portions of the gate electrode and the gate spacers.

14. A method as defined by claim 13 , wherein the protection film includes a stack of a buffer oxide film and a nitride film.

15. A method as defined by claim 14 , wherein portions of upper portions of the nitride film and the gate spacers are etched by wet etching with a chemical, or dry etching.

16. A method as defined by claim 15 , wherein the chemical includes hot phosphoric acid.

17. A method as defined by claim 15 , wherein the dry etching is performed by using a combination of an F-group gas, such as CF 4 , SF 6 , or NF 3 , and an additive gas of O 2 , N 2 , Ar, or He.

18. A method as defined by claim 14 , wherein the buffer oxide film is removed by wet etching with a chemical containing HF, or dry etching.

19. A method as defined by claim 1 , wherein the salicide forming metal is one selected from Ti, TiN, Co, Ni, Pt, and W.