Granted Patent B1

US 7,577,784 · App. 11/011,464 · Granted Aug 18, 2009

Abstract

Claims (45)

1. A memory system comprising:

a plurality row decoders logically divided into row decoder groups, each row decoder corresponding to a different mask field of a full ternary content addressable memory (TCAM) array, each mask field having a unique row address; and

an address modification circuit coupled to each row decoder group, each address modification circuit having

a first mode that enables the writing of a same mask value simultaneously to the corresponding mask fields of a plurality of row decoders of the group in response to any of the unique addresses of the corresponding mask fields of the group, and

a second mode that enables the writing of one mask value to one corresponding mask field in response to the unique address of the one mask field; wherein

each row decoder has inputs coupled to the address modification circuit corresponding to its row decoder group, and an output coupled to a corresponding word line.

2. The memory system of claim 1 , wherein:

each address modification circuit is placed into the first mode in response to a write-to-mask command.

3. The memory system of claim 1 , wherein:

each mask field forms part of a memory location that further includes a data field for storing a data value.

4. The memory system of claim 1 , wherein:

each address modification circuit further includes a configuration circuit adapted to alter the number of mask fields to which the same mask value is written in the first mode in response to at least a second control signal received in the configuration circuit.

5. The memory system of claim 1 , further including:

the number of mask fields is eight.

6. The memory system of claim 1 , further including:

the memory system is coupled to a network search engine.

7. A method of operating a memory system, comprising the steps of:

receiving a unique address corresponding to a memory location;

in a pseudo-ternary mode, modifying at least a portion of the unique address to activate a predetermined number of N word lines, where N is an integer greater than 1, to write a mask value simultaneously into mask fields of a plurality of memory locations of a full ternary CAM array, the memory locations having different addresses and one of the memory locations having the unique address; and

in a full ternary mode, activating one word line to write one mask value into the mask field of the memory location of the full ternary CAM array that has the unique address.

8. The method of claim 7 , wherein:

receiving a unique address includes coupling at least a portion of a unique row address to control logic of the memory system.

9. The method of claim 7 , wherein:

each memory location of the fully ternary CAM array includes a data field corresponding to each mask field, the data field storing data values for comparison with compare data.

10. The method of claim 7 , further including:

receiving the mask value on bit lines associated with the plurality of memory locations.

11. The method of claim 7 , further including:

receiving a write-to-mask command in conjunction with the unique address.

12. The method of claim 7 , further including:

in the pseudo-ternary mode, prior to activating the predetermined number of N word lines, specifying the value N.

13. The method of claim 12 , wherein:

the value of N=2 m , where m is greater than zero.

14. A system, comprising:

a ternary content addressable memory (CAM) array having a plurality of mask locations each coupled to a corresponding mask word line;

a row decoder coupled to each mask word line, each row decoder having decoder inputs coupled to receive address values and a decoder output; and

control logic coupled to the row decoders that enables either multiple mask word lines or one mask word line to be driven to an active level in response to a unique address and includes an address modifier circuit that receives address values and modifies the address values applied to the decoder inputs of the row decoders in response to a pseudo ternary mode signal having a first value, and applies unmodified address values to the decoder inputs of the row decoders in response to the pseudo ternary mode signal having a second value.

15. The system of claim 14 , wherein:

each row decoder is coupled to a same set of address lines: and

the address modifier circuit drives a predetermined number of the address lines to predetermined values regardless of the received address values in response to the pseudo ternary mode signal having the first value.

16. The system of claim 14 , wherein:

the control logic further includes

a decoder modification circuit corresponding to each row decoder, each decoder modification circuit having at least a first modifier input coupled the decoder output of the corresponding row decoder and an output coupled to one of the mask word lines, a second modifier input of a plurality of decoder modification circuits being commonly coupled to a same pseudo select mode line.

17. The system of claim 16 , wherein:

the address values received by each row decoder include less significant bits (LSBs) of an address and more significant bits (MSBs) of the address; and

the pseudo select mode line receives a signal generated by decoding the MSBs of the address.

Assignments (12)