Scalable integrated circuit high density capacitors
View Patent ↗The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
1. A scalable integrated circuit capacitor, comprising:
a first metal layer and a second metal layer each including a first metallization pattern and a second metallization pattern, said first metallization pattern and said second metallization patterns each having a plurality of finger tracks approximately perpendicular to a backbone track wherein said plurality of finger tracks of said first metallization pattern are interlaced with said plurality of finger tracks of said second metallization pattern; and
a via layer including a plurality of vias that connect said plurality of finger tracks of said first metallization pattern of said first metal layer to said plurality of finger tracks of said first metallization pattern of said second metal layer and said plurality of finger tracks of said second metallization pattern of said first metal layer to said plurality of finger tracks of said second metallization pattern of said second metal layer.
2. The capacitor of claim 1 , wherein said plurality of finger tracks of said first metallization pattern of said first metal layer are staggered with respect to said plurality of finger tracks of said first metallization pattern of said second metal layer.
3. The capacitor of claim 1 , wherein said plurality of finger tracks of said first metallization pattern of said first metal layer are rotated approximately ninety degrees with respect to said plurality of finger tracks of said first metallization pattern of said second metal layer.
4. The capacitor of claim 1 , wherein said plurality of vias couple said backbone track of said first metallization pattern of said first metal layer to said backbone track of said first metallization pattern of said second metal layer and said backbone track of said second metallization pattern of said first metal layer to said backbone track of said second metallization pattern of said second metal layer.
5. The capacitor of claim 1 , further comprising:
a shield proximate to said first metal layer that reduces unwanted parasitic capacitance.
6. The capacitor of claim 5 , wherein said shield is coupled to said first metallization pattern of said first metal layer.