Granted Patent B1

US 7,149,101 · App. 11/014,123 · Granted Dec 12, 2006

Abstract

Claims (62)

1. A content addressable memory (CAM) device, comprising:

a plurality of CAM blocks, each CAM block comprising a plurality of CAM entries and having an active mode that consumes more current than an idle mode;

a command control block that receives command data; and

a dummy control circuit coupled to at least one CAM block that initiates a dummy operation in the at least one CAM block in response to selected command data prior to an actual operation corresponding to the command data.

2. The CAM device of claim 1 , wherein:

the command data comprises a search command and a search key; and

the dummy control circuit initiates a dummy search operation in the at least one CAM block in response to the search command, and prior to the search key being applied to the at least one CAM block.

3. The CAM device of claim 1 , wherein:

the plurality of CAM blocks are divided into at least a first section and second section; and

the dummy control circuit comprises at least one multiplexer (MUX) that selects between a valid search command and a dummy search command.

4. The CAM device of claim 1 , wherein:

the command control block comprises a decoder that generates a search command; and

the dummy control circuit comprises a block command decoder coupled to selected CAM blocks, each block command decoder activating the respective CAM block in response to a dummy search command.

5. The CAM device of claim 1 , wherein:

the command control block comprises a decoder and a dummy control circuit coupled to receive the command data that issues a dummy search command followed by an actual search command in response to a search request in the command data.

6. The CAM device of claim 1 , further including:

the dummy control circuit comprises a dummy signal activation circuit that sequentially activates at least one dummy activation signal in response to a search request in the command data; and

an activation circuit coupled to at least one CAM block that activates the at least one CAM block in response to the at least one dummy activation signal.

7. The CAM device of claim 1 , wherein:

the plurality of CAM blocks includes at least four CAM blocks;

the command control block receives command data according to a periodic clock signal, and in response to a sequence of search requests activates a first CAM block in a first actual search cycle and more than two CAM blocks in a second actual search cycle; and

the dummy control circuit activates one CAM block with a dummy search prior to the first search cycle and a second CAM block with the dummy search in the first search cycle.

8. The CAM device of claim 1 , wherein:

the plurality of CAM blocks includes at least six CAM blocks;

the command control block receives command data according to a periodic clock signal, and in response to a sequence of search requests activates a first CAM block in a first search cycle and activates, first, second and third CAM blocks in a second search cycle; and

the dummy control circuit activates one CAM block with a dummy search two cycles prior to the first search cycle, and activates two CAM blocks with a dummy search one cycle prior to the first search cycle.

9. The CAM device of claim 1 , further including:

the plurality of CAM blocks are arranged into a plurality of sections, each section including at least a first CAM block and a second CAM block separated by an activation control circuit; wherein

each activation control circuit selectively activates CAM entries in the corresponding second CAM block based on search results of a corresponding entries in the first CAM block.

10. A content addressable memory (CAM) device, comprising:

a first section comprising at least a first CAM block coupled to a first command data bus and a second CAM block coupled to the first command data bus by first block register;

a second section, comprising at least a second command data bus coupled to the first command data bus by a first section register, a third CAM block coupled to the second command data bus, and a fourth CAM block coupled to the second command data bus by second block register; and

a control block that receives search command data, and in response to a search requests, outputs a dummy search command that is not required to generate valid search result data followed by an actual search command that generates valid search result data.

11. The CAM device of claim 10 , wherein:

the first section includes a first section priority encoder having a first input coupled to a result output of the first CAM block by a first output register, and a second input coupled to a result output of the second CAM block; and

the second section includes a second section priority encoder having a first input coupled to a result output of the third CAM block by a second output register, and a second input coupled to a result output of the fourth CAM block.

12. The CAM device of claim 11 , further including:

a global priority encoder having a first input coupled to an output of the first section priority encoder by a first output register, and a second input coupled to an output of the second section priority encoder.

13. The CAM device of claim 10 , wherein:

the first block register, first section register, and second block register are commonly controlled by a same clock signal.

14. A method of activating a content addressable memory (CAM) device in response to command data, comprising the steps of:

(a) receiving at least one command;

(b) sequentially activating an increasing number of CAM blocks in a sequence according to the at least one command; and

(c) activating at least one CAM block prior to the start of the sequence and during the sequence according to a dummy activation operation that is not required to generate valid output data from the respective CAM block.

15. The method of claim 14 , wherein:

the step (a) further includes decoding command data, and generating the dummy search command for one clock cycle, and generating an actual search command on the next clock cycle.

16. The method of claim 14 , wherein:

the step (a) further includes receiving a series of consecutive search commands; and

each step of the sequence occurs in one clock cycle, and only one CAM block is switched to an active state in a given clock cycle until all the CAM blocks are in the active state.

17. The method of claim 14 , wherein:

the step (c) includes issuing a dummy search to selected CAM blocks, and not other CAM blocks.

18. The method of claim 14 , wherein:

the step (c) includes issuing a dummy search to a plurality of CAM blocks, and activating selected of the CAM blocks in response to the dummy search, while not activating other of the CAM blocks in response to the dummy search.

19. The method of claim 14 , wherein:

the step (c) includes

generating a plurality of dummy activation signals, at least a first activation signal being activated prior to the search sequence, and

activating a different CAM block in response to each dummy activation signal.

20. The method of claim 14 , further including:

logically arranging CAM blocks into sections, each section including at least a first CAM block and a second CAM block; and

step (b) includes, in a search operation, sequentially applying a search key to each section, and within each section, applying a first portion of the search key to the first CAM block and a second portion of the search key to the second CAM block.

21. The method of claim 14 , further including:

sequentially de-activating an increasing number of CAM blocks in a sequence, in response to a predetermined number of idle periods.

Assignments (12)