Method for providing layout design and photo mask
View Patent ↗A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the closed mesh point having the hole pattern thereon.
1. A method for providing a layout design for a semiconductor integrated circuit, comprising:
disposing a hole pattern at a mesh point of orthogonally intersecting virtual grid lines of a virtual grid,
wherein each adjacent mesh point is free of another hole pattern, said adjacent mesh point being closest to a hole mesh point, said hole mesh point having said hole pattern thereon.
2. The method according to claim 1 , wherein a size of a mesh of said virtual grid is smaller than a resolution limit pitch for said hole pattern in an exposure process for said semiconductor integrated circuit.
3. The method according to claim 2 , wherein a mesh point within a circle except said hole mesh point having said hole pattern thereon is free of another hole pattern, said circle having a center at said hole mesh point and having a radius being equivalent to a closest pitch, the closest pitch being a minimum pitch for disposing said hole pattern.
4. A photo mask employed for an exposure process for the semiconductor integrated circuit that is designed by the method for providing the layout design thereof according to claim 1 ,
wherein a hole pattern is disposed at a hole mesh point of the virtual grid on the photo mask, and
wherein a supplementary pattern is disposed at some of the mesh points having no hole pattern thereon, said supplementary pattern having smaller dimension such that the pattern thereof is not transferred to the photo resist.
5. The photo mask according to claim 4 , wherein a size of a mesh of said virtual grid is smaller than a resolution limit pitch for said hole pattern in an exposure process for said semiconductor integrated circuit.
6. The photo mask according to claim 5 , wherein a mesh point within a circle other than said hole mesh point is free of another hole pattern, said circle having a center at said hole mesh point and having a radius being equivalent to a closest pitch, the closest pitch being a minimum pitch for disposing said hole pattern.
7. The photo mask according to claim 4 , wherein a mesh point that is not an adjacent mesh point has said supplementary pattern thereon, said adjacent mesh point being closest to said hole mesh point having said hole pattern thereon.
8. The photo mask according to claim 7 , wherein an adjacent mesh point is free of another supplementary pattern, said adjacent mesh point being closest to said mesh point having said supplementary pattern thereon.
9. The photo mask according to claim 8 , wherein said adjacent mesh point is free of another supplementary pattern, said adjacent mesh point being closest to a mesh point having a supplementary pattern thereon, said supplementary pattern being disposed at a position that is away from a hole mesh point having said hole pattern thereon by a distance equivalent to integer-number folds of a closest pitch, said closest pitch being a minimum pitch for disposing said hole pattern.
10. The photo mask according to claim 9 , wherein a mesh point within circles except said hole mesh point having said hole pattern thereon and except said mesh point having said supplementary pattern thereon is free of said supplementary pattern, one of said circles having a center at said hole mesh point and the other of said circles having a center at a mesh point having said supplementary pattern thereon and both circles having a radius being equivalent to said resolution limit pitch.
11. A method for providing a layout design for a semiconductor integrated circuit, comprising:
disposing a hole pattern at a mesh point, which is an intersecting point of mutually orthogonal virtual grid lines, wherein an interval of one of arrays disposed along the virtual grid lines in mutually orthogonal two directions is smaller than a resolution limit pitch of an exposure process for said semiconductor device and an interval of the other array thereof is a size equal to or larger than said resolution limit pitch, and wherein, when said hole pattern is disposed at a mesh point of said virtual grid, concerning the direction along said array having the interval smaller than said resolution limit pitch, no hole pattern is disposed at an adjacent mesh point that is closest to said mesh point having said hole pattern thereon.
12. The method according to claim 11 , wherein a mesh point within a circle other than said hole mesh point having said hole pattern thereon is free of another hole pattern, said circle having a center at said hole mesh point and having a radius being equivalent to a closest pitch, the closest pitch being a minimum pitch for disposing said hole pattern.
13. A photo mask employed for an exposure process for the semiconductor integrated circuit designed by the method for providing the layout design thereof according to claim 11 ,
wherein a hole pattern is disposed at a hole mesh point of the virtual grid on the photo mask, and
wherein a supplementary pattern is disposed at some of the mesh points having no hole pattern thereon, said supplementary pattern having smaller dimension such that the pattern thereof is not transferred to the photo resist.
14. The photo mask according to claim 13 , wherein a mesh point within a circle other than said hole mesh point having said hole pattern thereon is free of another hole pattern, said circle having a center at said hole mesh point and having a radius being equivalent to a closest pitch, the closest pitch being a minimum pitch for disposing said hole pattern.
15. The photo mask according to claim 13 ,
wherein, in the virtual grid on said photo mask, said hole pattern is disposed at a hole mesh point of said virtual grid, and
wherein, concerning the direction along said array having the interval smaller than said resolution limit pitch, no supplementary pattern is disposed at an adjacent mesh point that is closest to said mesh point having said hole pattern thereon.
16. The photo mask according to claim 15 ,
wherein, in the virtual grid on said photo mask, said supplementary pattern is disposed at a mesh point of said virtual grid, and
wherein, concerning the direction along said array having the interval smaller than said resolution limit pitch, no supplementary pattern is disposed at an adjacent mesh point that is closest to said mesh point having said supplementary pattern thereon.