IPHD (iterative parallel hybrid decoding) of various MLC (multi-level code) signals
View Patent ↗IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.
1. A decoder that is operable to perform IPHD (Iterative Parallel Hybrid Decoding) on a MLC (Multi-Level Code) LDPC (Low Density Parity Check) signal, the decoder comprising:
an initialize edge message functional block that is operable to:
receive I, Q (In-phase, Quadrature) values corresponding to a symbol of the MLC LDPC signal; and
initialize a plurality of edge messages with respect to a plurality of bit nodes to a plurality of predetermined values for each level of the MLC LDPC signal;
a plurality of check engines in a parallel arrangement that includes a separate check engine that corresponds to each level of the MLC LDPC signal that is operable to:
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to receive the initialized plurality of edge messages with respect to a plurality of bit nodes from the initialize edge message functional block; and
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines is operable to perform check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes;
a symbol update engine that is operable to:
for each level of the MLC LDPC signal, receive the updated plurality of edge messages with respect to the plurality of check nodes from the plurality of check engines;
receive the I, Q values corresponding to the symbol of the MLC LDPC signal;
calculate a plurality of symbol metrics using the I, Q values;
calculate a plurality of LLR (Log-Likelihood Ratio) bit metrics using the plurality of symbol metrics;
calculate a plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using the plurality of LLR bit metrics and the updated pluralities of edge messages with respect to the plurality of check nodes corresponding to all levels of the MLC LDPC signal; and
estimate a logarithm of a probability of the symbol of the MLC LDPC signal using the plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using and at least one symbol metric of the plurality of symbol metrics; and
a plurality of bit engines in a parallel arrangement that includes a separate bit engine that corresponds to each level of the MLC LDPC signal that is operable to:
receive the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal;
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to receive the updated plurality of edge messages with respect to the plurality of check nodes; and
for each level of the MLC LDPC signal, the corresponding bit engine of the plurality of bit engines is operable to perform bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes.
2. The decoder of claim 1 , wherein:
the symbol update engine is operable to make a hard decision of the symbol of the MLC LDPC signal using the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal during each decoding iteration of a plurality of decoding iterations.
3. The decoder of claim 2 , wherein:
the plurality of bit engines is operable to perform syndrome checking using the hard decision of the symbol of the MLC LDPC signal to determine whether each syndrome of a plurality of syndromes of an LDPC code by which the MLC LDPC signal is generated is equal to zero.
4. The decoder of claim 3 , wherein:
a final decoding iteration of the plurality of decoding iterations is determined when each syndrome of the plurality of syndromes of the LDPC code by which the MLC LDPC signal is generated is equal to zero.
5. The decoder of claim 1 , wherein:
the plurality of LLR bit metrics is calculated using min* (min-star) processing or max* (max-star) processing.
6. The decoder of claim 1 , wherein:
for each level of the MLC LDPC signal, the corresponding check engine of the plurality of check engines performs check node processing that involves updating the plurality of edge messages with respect to the plurality of check nodes using min* (min-star) processing or max* (max-star) processing.
7. The decoder of claim 1 , wherein:
the decoder performs a predetermined plurality of decoding iterations.
8. The decoder of claim 1 , wherein:
the plurality of predetermined values to which the plurality of edge messages with respect to the plurality of bit nodes is initialized is a plurality of values of equal likelihood.
9. The decoder of claim 1 , wherein:
the MLC LDPC signal includes a plurality of symbols;
the symbol of the MLC LDPC signal is mapped according to a first modulation that includes a first constellation shape and a corresponding first mapping of the constellation points within the first constellation shape; and
at least one additional symbol of the MLC LDPC signal is mapped according to a second modulation that includes a second constellation shape and a corresponding second mapping of the constellation points within the second constellation shape.
10. The decoder of claim 9 , wherein:
at least one of the corresponding first mapping and the corresponding second mapping is a Gray code mapping.
11. The decoder of claim 9 , wherein:
at least one of the corresponding first mapping and the corresponding second mapping is a non-Gray code mapping.
12. The decoder of claim 9 , wherein:
at least one of the corresponding first modulation and the second modulation is an 8 PSK (Phase Shift Key) modulation.
13. A method for performing IPHD (Iterative Parallel Hybrid Decoding) on a MLC (Multi-Level Code) LDPC (Low Density Parity Check) signal, the method comprising:
receiving I, Q (In-phase, Quadrature) values corresponding to a symbol of the MLC LDPC signal;
initializing a plurality of edge messages with respect to a plurality of bit nodes to a plurality of predetermined values for each level of the MLC LDPC signal;
for each level of the MLC LDPC signal, receiving the initialized plurality of edge messages with respect to a plurality of bit nodes from the initialize edge message functional block;
for each level of the MLC LDPC signal, performing check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes;
for each level of the MLC LDPC signal, receiving the updated plurality of edge messages with respect to the plurality of check nodes;
calculating a plurality of symbol metrics using the I, Q values;
calculating a plurality of LLR (Log-Likelihood Ratio) bit metrics using the plurality of symbol metrics;
calculating a plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using the plurality of LLR bit metrics and the updated pluralities of edge messages with respect to the plurality of check nodes corresponding to all levels of the MLC LDPC signal;
estimating a logarithm of a probability of the symbol of the MLC LDPC signal using the plurality of logarithms of probabilities of bits of the symbol of the MLC LDPC signal using and at least one symbol metric of the plurality of symbol metrics;
receiving the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal;
for each level of the MLC LDPC signal, receiving the updated plurality of edge messages with respect to the plurality of check nodes; and
for each level of the MLC LDPC signal, performing bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes.
14. The method of claim 13 , further comprising:
making a hard decision of the symbol of the MLC LDPC signal using the estimate of the logarithm of the probability of the symbol of the MLC LDPC signal during each decoding iteration of a plurality of decoding iterations.
15. The method of claim 14 , further comprising
performing syndrome checking using the hard decision of the symbol of the MLC LDPC signal to determine whether each syndrome of a plurality of syndromes of an LDPC code by which the MLC LDPC signal is generated is equal to zero.
16. The method of claim 15 , further comprising
determining a final decoding iteration of the plurality of decoding iterations when each syndrome of the plurality of syndromes of the LDPC code by which the MLC LDPC signal is generated is equal to zero.
17. The method of claim 13 , further comprising:
calculating the plurality of LLR bit metrics using min* (min-star) processing or max* (max-star) processing.
18. The method of claim 13 , further comprising:
for each level of the MLC LDPC signal, performing check node processing that involves updating the plurality of edge messages with respect to the plurality of check nodes using min* (min-star) processing or max* (max-star) processing.
19. The method of claim 13 , further comprising:
performing a predetermined plurality of decoding iterations.
20. The method of claim 13 , wherein:
the plurality of predetermined values to which the plurality of edge messages with respect to the plurality of bit nodes is initialized is a plurality of values of equal likelihood.
21. The method of claim 13 , wherein:
the MLC LDPC signal includes a plurality of symbols;
the symbol of the MLC LDPC signal is mapped according to a first modulation that includes a first constellation shape and a corresponding first mapping of the constellation points within the first constellation shape; and
at least one additional symbol of the MLC LDPC signal is mapped according to a second modulation that includes a second constellation shape and a corresponding second mapping of the constellation points within the second constellation shape.
22. The method of claim 21 , wherein:
at least one of the corresponding first mapping and the corresponding second mapping is a Gray code mapping.
23. The method of claim 21 , wherein:
at least one of the corresponding first mapping and the corresponding second mapping is a non-Gray code mapping.
24. The method of claim 21 , wherein:
at least one of the corresponding first modulation and the second modulation is an 8 PSK (Phase Shift Key) modulation.