IP Library Granted Patent US 7,105,370
Granted Patent B2
US 7,105,370 · App. 11/017,615 · Granted Sep 12, 2006

Method for fabricating a radiation-emitting semiconductor chip based on III-V nitride semiconductor

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Quick Facts
Patent No.
US 7,105,370
App. No.
11/017,615
Granted
Sep 12, 2006
Kind
B2
Abstract

A method for fabricating a radiation-emitting semiconductor chip having a thin-film element based on III–V nitride semiconductor material includes the steps of depositing a layer sequence of a thin-film element on an epitaxy substrate. The thin-film element is joined to a carrier, and the epitaxy substrate is removed from the thin-film element. The epitaxy substrate has a substrate body made from PolySiC or PolyGaN or from SiC, GaN or sapphire, which is joined to a grown-on layer by a bonding layer, and on which the layer sequence of the thin-film element is deposited by epitaxy.

Claims (61)

1. A method for fabricating a radiation-emitting semiconductor chip, which comprises the steps of:

providing an epitaxy substrate having a substrate body made from a material selected from the group consisting of PolySiC and PolyGaN, a bonding layer disposed on the substrate body, and a growth layer bonded to the substrate body by the bonding layer;

depositing a layer sequence forming a thin-film element on the growth layer by epitaxy, the thin-film element being based on a III–V nitride semiconductor material;

joining the thin-film element to a carrier; and

removing the epitaxy substrate from the thin-film element.

2. The method according to claim 1 , which further comprises forming the growth layer with an Si(111) layer.

3. The method according to claim 1 , which further comprises forming the bonding layer from a material selected from the group consisting of silicon oxide and silicon nitride.

4. The method according to claim 1 , which further comprises patterning the layer sequence forming the thin-film element into a plurality of individual thin-film elements which are separate from one another before the carrier is applied.

5. The method according to claim 1 , which further comprises forming a contact on the thin-film element after the epitaxy substrate has been removed.

6. The method according to claim 1 , which further comprises after the layer sequence has been applied, performing the steps of:

applying a temporary carrier to the layer sequence;

performing the step of removing the epitaxy substrate;

applying the carrier to that side of the layer sequence from which the epitaxy substrate has been removed; and

removing the temporary carrier.

7. The method according to claim 6 , which further comprises:

forming the layer sequence from a plurality of GaN-based layers; and patterning the layer sequence prior to an application of the temporary carrier.

8. The method according to claim 7 , which further comprises making a contact on the thin-film element after the temporary carrier has been removed.

9. The method according to claim 1 , which further comprises forming the layer sequence with an electrically conductive buffer layer formed on a surface of the growth layer.

10. The method according to claim 9 , which further comprises forming the electrically conductive buffer layer from a plurality of individual layers based on AlGaN.

11. The method according to claim 10 , which further comprises forming a first individual layer of the electrically conductive buffer layer which directly adjoins the growth layer with a higher Al content than a second individual layer which follows the first individual layer, as seen from the growth layer.

12. The method according to claim 11 , which further comprises forming a third individual layer of the individual layers on that side of the electrically conductive buffer layer which is remote from the grown-on layer and the third individual layer has a lower Al content than the second individual layer which precedes it, as seen from the growth layer.

13. The method according to claim 9 , which further comprises forming the electrically conductive buffer layer by the steps of:

applying a plurality of electrically conductive regions, disposed at a distance from one another, to the growth layer; and

applying a planarizing filler layer on the electrically conductive regions.

14. The method according to claim 13 , which further comprises forming the plurality of electrically conductive regions using a material selected from the group consisting of InGaN, GaN and InN.

15. The method according to claim 13 , which further comprises forming the filler layer with a material selected from the group consisting of AlGaN and AlGaInN, with an Al content which is so high that a planar layer is formed.

16. The method according to claim 1 , which further comprises forming a thickness of the grown-on layer to between approximately 1 μm and 20 μm.

17. The method according to claim 1 , which further comprises forming a thickness of the grown-on layer to be less than 10 μm.

18. The method according to claim 1 , which further comprises forming the epitaxy substrate with a coefficient of thermal expansion matched to a material of the thin-film element.

19. The method according to claim 1 , which further comprises forming the epitaxy substrate with a coefficient of thermal expansion which is greater than a material of the thin-film element.

20. A method for fabricating a radiation-emitting semiconductor chip, which comprises the steps of:

providing an epitaxy substrate having a substrate body formed from a material selected from the group consisting of SiC, GaN and sapphire, a bonding layer disposed on the substrate body, and a growth layer bonded to the substrate body by the bonding layer;

depositing a layer sequence forming a thin-film element on the growth layer by epitaxy, the thin-film element being based on a III–V nitride semiconductor material;

joining the thin-film element to a carrier; and

removing the epitaxy substrate from the thin-film element.

21. The method according to claim 20 , which further comprises forming the growth layer with an Si(111) layer.

22. The method according to claim 20 , which further comprises forming the bonding layer from a material selected from the group consisting of silicon oxide and silicon nitride.

23. The method according to claim 20 , which further comprises patterning the layer sequence forming the thin-film element into a plurality of individual thin-film elements which are separate from one another before the carrier is applied.

24. The method according to claim 20 , which further comprises forming a contact on the thin-film element after the epitaxy substrate has been removed.

25. The method according to claim 20 , which further comprises after the layer sequence has been applied, performing the steps of:

applying a temporary carrier to the layer sequence;

performing the step of removing the epitaxy substrate;

applying the carrier to that side of the layer sequence from which the epitaxy substrate has been removed; and

removing the temporary carrier.

26. The method according to claim 25 , which further comprises:

forming the layer sequence from a plurality of GaN-based layers; and

patterning the layer sequence prior to an application of the temporary carrier.

27. The method according to claim 26 , which further comprises making a contact on the thin-film element after the temporary carrier has been removed.

28. The method according to claim 20 , which further comprises forming the layer sequence with an electrically conductive buffer layer formed on a surface of the growth layer.

29. The method according to claim 28 , which further comprises forming the electrically conductive buffer layer from a plurality of individual layers based on AlGaN.

30. The method according to claim 29 , which further comprises forming a first individual layer of the electrically conductive buffer layer which directly adjoins the growth layer with a higher Al content than a second individual layer which follows the first individual layer, as seen from the growth layer.

31. The method according to claim 30 , which further comprises forming a third individual layer of the individual layers on that side of the electrically conductive buffer layer which is remote from the growth layer and the third individual layer a lower Al content than the second individual layer which precedes it, as seen from the growth layer.

32. The method according to claim 28 , which further comprises forming the electrically conductive buffer layer by the steps of:

applying a plurality of electrically conductive regions, disposed at a distance from one another, to the growth layer; and

applying a planarizing filler layer on the electrically conductive regions.

33. The method according to claim 32 , which further comprises forming the plurality of electrically conductive regions using a material selected from the group consisting of InGaN, GaN and InN.

34. The method according to claim 32 , which further comprises forming the filler layer with a material selected from the group consisting of AlGaN and AlGaInN, with an Al content which is so high that a planar layer is formed.

35. The method according to claim 20 , which further comprises forming a thickness of the growth layer to between approximately 1 μm and 20 μm.

36. The method according to claim 20 , which further comprises forming a thickness of the growth layer to be less than 10 μm.

37. The method according to claim 20 , which further comprises forming the epitaxy substrate with a coefficient of thermal expansion matched to a material of the thin-film element.

38. The method according to claim 20 , which further comprises forming the epitaxy substrate with a coefficient of thermal expansion being greater than a material of the thin-film element.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2020
From: OSRAM OPTO SEMICONDUCTORS GMBH
To: OSRAM OLED GMBH
Reel/Frame 051467/0906 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2019
From: OSRAM GMBH
To: OSRAM OPTO SEMICONDUCTORS GMBH
Reel/Frame 051381/0694 →