Method of fabricating thin film transistor
View Patent ↗Disclosed is a method of fabricating a thin film transistor in which, in order to control the concentration of metal catalysts remaining on a polycrystalline silicon layer when an amorphous silicon layer formed on an insulating substrate is crystallized into the polycrystalline silicon layer by a super grain silicon (SGS) crystallization method, the substrate is annealed so that a very small amount of metal catalyst is adsorbed or diffused into a capping layer, and then a crystallization process is carried out, thereby minimizing the concentration of the metal catalysts remaining on the polycrystalline silicon layer, as well as forming a thick metal catalyst layer. The method includes preparing an insulating substrate; sequentially forming an amorphous silicon layer, a capping layer, and a metal catalyst layer on the substrate; first annealing the substrate to adsorb or diffuse metal catalysts into the capping layer; removing the metal catalyst layer; second annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer by means of the metal catalyst; and removing the capping layer. Thus, with the method of fabricating the thin film transistor of the present invention, it is possible to minimize the concentration of the metal catalysts remaining on the polycrystalline silicon layer, as well as to form a thick metal catalyst layer.
1. A method of fabricating a thin film transistor, comprising:
preparing an insulating substrate;
sequentially forming an amorphous silicon layer, a capping layer, and a metal catalyst layer on the substrate;
first annealing the substrate, adsorbing or diffusing a metal catalyst of the metal catalyst layer into the capping layer;
completely removing the metal catalyst layer after first annealing the substrate and before second annealing the substrate;
second annealing the substrate, crystallizing the amorphous silicon layer into a polycrystalline silicon layer by means of the metal catalyst that is adsorbed or diffused into the capping layer; and
removing the capping layer.
2. The method according to claim 1 , further comprising:
after removing the capping layer,
patterning the polycrystalline silicon layer, forming a semiconductor layer; and
forming a gate insulating layer, a gate electrode, an interlayer insulting film, and source and drain electrodes on the semiconductor layer.
3. The method according to claim 1 , wherein the capping layer is formed of an insulating layer.
4. The method according to claim 1 , wherein the capping layer is formed of silicon nitride (SiN x ).
5. The method according to claim 1 , wherein the first annealing is any one of a rapid thermal annealing (RTA) process and a laser irradiation process.
6. The method according to claim 1 , wherein the first annealing is performed at a temperature of 200 to 600° C.
7. The method according to claim 1 , wherein the metal catalyst layer contains at least one selected from a group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt.
8. The method according to claim 1 , wherein the metal catalyst layer contains at least Ni.
9. The method according to claim 1 , wherein the metal catalyst layer has a thickness of 200 to 1000 Å.
10. The method according to claim 1 , wherein the metal catalyst has a concentration of 1×10 10 to 1×10 12 atoms/cm 3 .
11. The method according to claim 1 , wherein the second annealing is performed at a temperature of 400 to 1300° C.
12. A method of fabricating a thin film transistor, comprising:
arranging an amorphous silicon layer on a substrate;
arranging a capping layer on the amorphous silicon layer;
arranging a metal catalyst layer on the capping layer;
annealing, introducing a metal catalyst of the metal catalyst layer into the capping layer;
completely removing the metal catalyst layer; and
annealing, forming a polycrystalline silicon layer from the amorphous silicon layer by means of the metal catalyst introduced into the capping layer after completely removing the metal catalyst layer.
13. The method according to claim 12 , further comprising:
removing the capping layer;
patterning the polycrystalline silicon layer, forming a semiconductor layer; and
forming a gate insulating layer, a gate electrode, an interlayer insulting film, and source and drain electrodes on the semiconductor layer.
14. The method according to claim 12 , wherein the capping layer is formed of an insulating layer.
15. The method according to claim 12 , wherein the capping layer is formed of silicon nitride (SiN x ).
16. The method according to claim 12 , wherein the annealing, introducing the metal catalyst into the capping layer is any one of a rapid thermal annealing (RTA) process and a laser irradiation process.
17. The method according to claim 12 , wherein the annealing, introducing the metal catalyst into the capping layer is performed at a temperature of 200 to 600° C., and the annealing, forming the polycrystalline silicon layer is performed at a temperature of 400 to 1300° C.
18. The method according to claim 12 , wherein the metal catalyst layer contains at least one selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt.
19. The method according to claim 12 , wherein the metal catalyst layer has a thickness of 200 to 1000 Å.
20. The method according to claim 12 , wherein the metal catalyst has a concentration of 1×10 10 to 1×10 12 atoms/cm 3 .