Semiconductor device and fabrication method thereof
View Patent ↗On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
1. A semiconductor device comprising:
lower electrode;
capacitor insulation layer provided on an entire upper surface of said lower electrode; and
an upper electrode provided on a first portion of said capacitor insulation layer, a thickness of said capacitor insulation layer in the first portion below said upper electrode being thicker than that in a second portion of said capacitor insulation layer, wherein said upper electrode, said capacitor insulation layer, and said lower electrode constitute a capacitor element in an area of the first portion of said capacitor insulation layer,
wherein said capacitor insulation layer is a homogenous material,
wherein a thickness of the second portion of said capacitor insulation layer is 10 to 40 nanometers,
wherein the lower layer wiring is formed in the same layer as the capacitor lower electrode.
2. The semiconductor device according to claim 1 , further comprising a lower wiring formed by patterning a conductive layer with said lower electrode, said capacitor insulation layer being also provided on an entire upper surface of said lower wiring, and the thickness of said capacitor insulation layer in a region directly above said lower wiring being thinner than in the first portion of said capacitor insulation layer directly below said upper electrode.
3. The semiconductor device according to claim 1 , further comprising: a semiconductor substrate; and an insulation layer provided on said semiconductor substrate, said lower electrode being provided on said insulation layer.
4. A method for fabricating a semiconductor device, the method comprising:
forming a first conductive layer on a supporting substrate;
forming a capacitor-insulator layer as a homogenous material on said first conductive layer;
forming a second conductive layer on said capacitor-insulator layer;
forming a first resist pattern on said second conductive layer;
etching said second conductive layer for selectively removing said second conductive layer by using said first resist pattern as a mask, to obtain an upper electrode formed by said second conductive layer, and etching said capacitor-insulator layer for selectively removing a portion of said capacitor-insulator layer not disposed below said second conductive layer in a thickness direction;
forming a second resist pattern to cover a region containing a region directly above said upper electrode; and
etching said capacitor-insulator layer for selectively removing a remaining part of said capacitor-insulator layer by using said second resist pattern as a mask, to obtain a capacitor insulation layer formed by said capacitor-insulator layer, and etching said first conductive layer for selectively removing said first conductive layer to obtain a lower electrode and a lower layer wiring formed by said first conductive layer,
wherein said etching of said capacitor-insulation layer using said first resist pattern is performed using a chlorine containing gas such that a thickness of said capacitor insulation layer ranges from 10 to 40 nanometers,
wherein said etching of said capacitor-insulation layer using said second resist pattern is performed using a chlorine-containing gas.
5. The method for fabricating a semiconductor device according to claim 4 , wherein the etching of said second conductive layer and the etching of said capacitor-insulator layer for selectively removing a part of said capacitor-insulating layer in the thickness direction are performed under a same condition.
6. The method for fabricating a semiconductor device according to claim 4 , wherein the etching of said capacitor-insulator layer and the etching of said first conductive layer are performed under a same condition.
7. The method for fabricating a semiconductor device according to claim 4 , further comprising depositing an insulation layer on a semiconductor substrate to form said supporting substrate.
8. A method for fabricating a semiconductor device, the method comprising:
providing a first conductive layer on a supporting substrate, a capacitor-insulator layer as a homogenous material on said first conductive layer, and a second conductive layer on said capacitor-insulator layer;
forming a first resist pattern on said second conductive layer;
etching said second conductive layer for selectively removing said second conductive layer by using said first resist pattern as a mask, to obtain an upper electrode formed by said second conductive layer, and etching said capacitor-insulator layer for selectively removing a portion of said capacitor-insulator layer not disposed below said second conductive layer in a thickness direction;
forming a second resist pattern to cover a region containing a region directly above said upper electrode; and
etching said capacitor-insulator layer for selectively removing a remaining part of said capacitor-insulator layer by using said second resist pattern as a mask, to obtain a capacitor insulation layer formed by said capacitor-insulator layer, and etching said first conductive layer for selectively removing said first conductive layer to obtain a lower electrode and a lower layer wiring formed by said first conductive layer,
wherein said etching of said capacitor-insulation layer using said first resist pattern is performed using a chlorine containing gas such that a thickness of said capacitor insulation layer is 10 to 40 nanometers,
wherein said etching of said capacitor-insulation layer using said second resist pattern is performed using a chlorine-containing gas.